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NCP1910GEVB

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28
PFCok Signal
The PFC provides a “PFCok” signal to:
• enable the dynamic response enhancer (I
VLD
) if V
bulk
is
below 95%, finish of the PFC soft-start,
• enable the PFC frequency foldback,
• enable the timer (t
DEL1
), which is to start the LLC-HB
converter,
• enable the timer (t
DEL2
), which is to stop LLC-HB
converter once “PFCok” is asserted low or V
bulk
is
lower than PG level after LLC-HB has started.
This “PFCok” signal is high when the PFC stage is in
normal operation, i.e. its output is above 95% of normal
output, and low otherwise.
Refer to Figure 54. “PFCok” signal is low when
• the PFC stage start-up, or
• any latch off signal arrives, or
• line brown-out activates.
“PFCok” signal is high when
• DRV starts operating and the PFC stage is above 95%
of target, i.e. the VLD comparator output is high, or
• the PFC stage is above 100% target, i.e. PFC
REG
comparator output is high.
Grand Reset
PFC_OK
Latch
S
R
Q
Q
PFC_BO
+
−
+
−
FB
V
PREF
95% V
PREF
VLD
PFC
REG
DRV
Figure 54. PFCok Signal Block Diagram
PFC Soft-Start
Refer to Figure 52 and 54. The device provides no PFC
driver output when the V
CTRL
is lower than V
CTRL(min)
.
V
CTRL
is pulled low by:
• V
CC
Under-Voltage Lockout, or
• Off Signal from On/Off Pin, or
• Thermal Shut-Down (TSD), or
• Line Brown-Out, or
• PFC Under-Voltage Protection
At one of these situations, NCP1910 grounds the V
CTRL
pin and turns off the 200 mA current source in regulation
block.
When the IC turns on again:
• V
CTRL
will be pulled low and PFC DRV output keeps
off until V
CTRL
is below V
CTRL(min)
to make PFC
starts with lowest duty cycle.
• The 200 mA current source block keeps off. Only the
Operating Transconductance Amplifier (OTA) raises
the V
CTRL
slowly.
This is to obtain a slow increasing duty cycle and hence
reduce the voltage and current stress on the MOSFET. A
soft-start operation is obtained.
PFC Under-Voltage Protection (UVP) for Open Loop
Protection
I
CC7
I
CC2
8% V
PREF
12% V
PREF
V
FB
Operating
Shutdown
Figure 55. PFC Under-Voltage Protection
As shown in Figure 55, when V
FB
is less than 8% of
V
PREF
, the device is shut down. The device automatically
starts operation when the output voltage goes above 12% of
V
PREF
. In normal situation of boost converter configuration,
the bulk voltage V
bulk
is always greater than the input
voltage V
in
and the feedback signal V
FB
has to be always
greater than 8% and 12% of V
PREF
to enable NCP1910 to
operate.
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29
The main purpose of this Under-Voltage Protection
function is to protect the power stage from damage at
feedback loop abnormal, such as V
FB
is grounded or the
feedback resistor R
FBU
is open.
Redundant Over-Voltage Protection (OVP2 pin)
Except the Over-Voltage Protection in FB pin, NCP1910
also reserve one dedicated pin, OVP2 pin, for the redundant
over voltage protection on bulk voltage. The purpose of this
feature is to protect the power components from damage in
case of any drift on the feedback resistor. As shown in
Figure 56, the OVP2 has 3 differences compared to the OVP
in FB pin:
• The protection mode provided by OVP2 pin is
latch-off. When OVP2 is triggered, the NCP1910 stays
at latch off mode, i.e. both PFC and LLC stop.
• A 20 ms filter is built-in after the OVP2 comparator for
better noise immunity.
• The reference voltage for this OVP2 comparator is
107% of V
PREF.
The resistance value of R
OVPU
and R
OVPL
could be the
same as R
FBU
and R
FBL
depending on the requirement of
OVP2 level. In this case, the level of the OVP in FB pin
would be 105% of normal bulk voltage and OVP2 will be
107% of normal bulk voltage. Or if one would need a higher
level for the OVP2, then it is flexible to change the value.
If someone doesn’t need this OVP2 feature, then OVP2
function could be disable by grounding the OVP2 pin.
R
OVPU
R
OVPL
C
OVP
107% V
PREF
PFC_OVP2
V
bulk
20 ms filter
OVP2
to SR-latch
Figure 56. PFC 2
nd
Over-Voltage Protection
PFC Abnormal
The PFC abnormal is detected by sensing V
CTRL
level.
When V
CTRL
stays at V
CTRL(max)
, or lower than V
CTRL(min)
– 0.1 V, for more than t
PFCabnormal
, PFC turns off first. After
t
DEL2
, LLC shuts down. It is latches off protection.
The main purpose of this feature is to avoid LLC from
operating without correct operation of PFC stage.
LLC Section
Current Controlled Oscillator (CCO)
The current controlled oscillator features a high-speed
circuitry allowing operation from 50 kHz up to 1 MHz.
However, as a D-flip-flop that creates division-by-two
internally provides two outputs (A and B in Figure 57), the
final effective signal on LLC driver outputs (ML and MU)
switches between 25 kHz and 500 kHz. The CCO is
configured in such a way that if the current that flows out
from the R
t
pin increases, the switching frequency also goes
up.
NCP1910
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VDD
+
-
S
R
Q
Q
Clk
D
B
A
Grand Reset
Latch
LLCenable
for ML
for MU
Grand Reset
S
R
Q
Q
Grand Reset
+
-
S
R
Q
Q
LLC_PG
Grand Reset
Disable LLC ML and MU
R
t
SS
R
min
R
max
R
SS
C
SS
Feedback
opto-coupler
C
t
I
DT
CS/FF > V
CS1
LLC_BO
t
DEL2
elapsed
V
SS_RST
Figure 57. The Current Controlled Oscillator Architecture and Configuration
V
Rt
V
Ctmax
The internal timing capacitor C
t
is charged by current
which is proportional to the current flowing out from the
R
t
pin. The discharging current i
DT
is applied when voltage
on this capacitor reaches V
Ctmax
. The output drivers are
disabled during discharge period so the dead time length is
given by the discharge current sink capability. Discharge
sink is disabled when voltage on the timing capacitor
reaches zero and charging cycle starts again. C
t
is grounded
to disable the oscillator when either of “turn-off LLC”
signals arrives.
For the resonant applications, it is necessary to adjust
minimum operating frequency with high accuracy. The
designer also needs to limit maximum operating and startup
frequency. All these parameters can be adjusted by using
external components connected to the R
t
pin as shown in
Figure 57.
The following approximate relationships hold for the
minimum, maximum and startup frequency respectively:
• The minimum switching frequency is given by the R
min
resistor value. This frequency is reached if there is no
feedback action and soft start period has already
elapsed.
R
min
+
490 10
6
V
Rt
F
min
(eq. 22)
• The maximum switching frequency excursion is limited
by the R
max
selection. Note that the maximum
frequency is influenced by the opto-coupler saturation
voltage value.
R
max
+
490 10
6
V
Rt
F
max
* F
min
(eq. 23)
• Resistor R
SS
together with capacitor C
SS
prepares the
soft start period for the resonant converter.
R
SS
+
490 10
6
V
Rt
F
SS
* F
min
(eq. 24)
Where:
♦ V
Rt
= 3.5 V
♦ F
min
is the minimal frequency
♦ F
max
is the maximal frequency
♦ F
SS
is the maximal soft start switching frequency
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NCP1910GEVB

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Buy NCP1910GEVB
Manufacturer:
ON Semiconductor
Description:
BOARD DEMO NCP1910DEMO-B-TLS
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