NCP1910GEVB Datasheet NCP1910A100DWR2G, NCP1910B100DWR2G, NCP1910A65DWR2G | P4-P6

NCP1910

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4

*It is recommended to separate the traces of power ground and analog ground. The analog ground traces for adjustment components are routed together first and then

connected to the ground pin (pin 17). The power ground for driving loop (PFC DRV and LLC ML) is connected from ground pin (pin 17) to the PFC sense resistor directly

and as short as possible.

Figure 3. Typical Application Schematic in B Version

M1

M2

C14

L2

D6

D9

T1

C4

Vo

ut

R11

R30

U1

C7

U2B

R10

R18

.

R9

R17

R8

R16

C3

Over Current

C15

R29

D12

D11

C13

R28

1

2

3

4

5

8

6

7

9

10

13

14

15

16

17

18

19

20

11

12

21

22

23

24

U100

C12

R22

R12

U2A

U3A

C10

0.1u

Bulk

12 V aux.

on/off

FB

Vcc

R21

Vref

Power

Good

C6

0.1u

R14R15

PG adj.

R13

BO level

R31

0.1

D4

D8

D3

D7

C5

D2

C1

L1

R19

10

D10

R20

10k

R1

3.5M

R2

1.5M

R32

3.6k

R4

2.2M

R5

3.5M

Input

Line

D5

D1

R23

120k

C8

0.22u

C2

R24

24k

R3

1.5M

R7

2.2M

R26

24k

C9

1u

R25

24k

R27

39k

C11

1n

R33

1.2k

R6

Vref

X2

PAD2

X3

V33V32

C16

0.1u

R34

8.4k

C17

1n

(*)

Q1

R35

300

C18

1n

R36

C19

skip

NCP1910

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5

+

−

+

−

VOVP

VUVP

105% Vpref

8% Vpref

PFC_OPL

+

−

OVP2

FB

95% Vpref

+

−

VLD

Vpref

VCTRL

OTA

Vctrl(min)

A

B

Multiplier

LBO

CS

VDD

VLBO^2

“1” BO NOTOK,

“0” BOK

A

B

A/B

ICS

A

B

Vctrl−Vctrl(min)

ICS x VLBO^2

+

−

+

−

ICS x VLBO > 275 uA

ICS > 200 uA

ICS

SUM 2

K1

K2

PFC_OL

VM

+

−

“0” / “1”

Vpref / 10%Vpref

S

R

Q

+

−

Vpref

PFC_OVP

PFC_OL

TSD

VLBO^2

VDD

IVLD

Dynamic

Response

Enhancer

“1” = UVP, “0” ok

Closed

if “1”

“1” OVP, “0” = ok

Vfold

ICS

Vdd

Oscillator section

ICt(min)

DRV

Vcc

foldback

PFC drive signal

Onoff

UVLO

Latch

RFB

pull down

“1” = OPL

“1” = OCP

PFC_UVP

The “PFC_OK” toggles high when:

− VLD is low

− PFC issues a driving pulse

The “PFC_OK” toggles low when:

− Vctrl stays out of window [Vctrl,min to

Vctrl,max] > 1 sec

− at this point, the latch is reset and the

“PFC_OK” output goes low.

“1” = below 5% reg

“0” ok

Auto−recovery internal OVP

+

−

VOVP2

107% Vpref

“1” OVP2, “0” = ok

Latched adjustable OVP2

PFC_OVP2

latched

Vctrl

+

−

Vctrl(min) − 0.1 V

Vctrl

+

−

1 sec

delay

If PFC issues an abnormal

situation, then latch off

Grand Reset

PFC_OK

S

R

Q

PFC_OK

Grand Reset

PFC_SKIP

(0.6 V clamp

voltage is

activated.)

VLBO

PFC_BO

+

−

ILBO

VLBOT

20 us filter

Latch

PFC_BO

PFC_SKIP

+

−

Vctrl(max)

PFCflag

ICt

Vfold(max)

Ict(fold)

S

R

Q

PFC_OVP

Grand Reset

PFC_OCP

PFC_OPL

Grand

Reset

“1” open

“0” close

PFC_abnormal

latched

PFC_BO

+

−

“1” = FB > Vpref

S

R

Q

Grand Reset

PFC_BO

Figure 4. Internal PFC Block Diagram

ICS VLBO

2

4

(

Vctrl * Vctrl

(

min

))

BO delay

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6

Rt

Vref

PG adj

PG out

CS/FF

on

/off

BO adj

Vcc

management

UVLO

Hi side

Level

shifter

Vrt

+

-

S

R

Q

Clk

D

Vboot

Mupper

Bridge

Vcc

Mlower

GND_LLC

delay

Dead time

A

B

A

PFC_FB

"1" BONOT OK

20 ms delay

tdel1

"1" enables LLC

"0" LLC is locked

Grand

Reset

SS

+

-

SS_RST

+

-

VCS1

+

-

VCS2

UVLO

Vdd

Vref

LLC_BO

Grand

Reset

S

R

Q

Grand Reset

Onoff

UVLO

PFC_BO

Grand Reset

Grand

Reset

R

Latch

Vdd

Rpull up

on_off

on/off

"1" controller is off

"0" controller is on

GND

Prop. delay

matching

PFC_UVP

PFC_OK

"1" is ok

"0" notok

5 ms delay

tdel2

R

"1" after reset

"0" when PG out

drops after 5 ms

PFC_OVP2

LLC_BO

Latch

Pulse

Trigger

S

R

CLK

Q

QN

S

R

Q

Skip/GND_PFC

+

-

Vskip

Skip: B version only

Thermal

Shut Down

TSD

"1" TSD is on

"0" TSD is off

Grand

Reset

"1" PGNOT OK

+

-

+

-

tBOK

tBONOTOK

LLC_BO

LLC_PG

S

R

Q

LLC_PG

Grand Reset

Figure 5. Internal LLC Block Diagram

NCP1910GEVB

NCP1910GEVB

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