Document Number: 001-89074 Rev. *L Page 3 of 30
Functional Description
The CY27410 is a standard-performance programmable clock
generator with four independent fractional PLLs, which
generates any frequency with a zero-ppm synthesis error. Each
PLL is followed by a set of four independent dividers to generate
four different frequencies from a single PLL. All four dividers are
synchronized to generate phase-aligned clock outputs with
minimal skew. The PLLs also support the spread-spectrum
feature to reduce EMI. PLL 1 has VCXO functionality to achieve
ppm granularity of output frequency.
The CY27410 accepts a crystal clock or a
single-ended/differential reference clock. The device supports
up to 12 outputs, divided into two banks with six outputs each.
Four outputs of PLL 1 and PLL 2 are multiplexed to
output Bank 1, and four clock outputs of PLL 3 and PLL 4 are
multiplexed to output Bank 2. The 12 outputs of the two banks
are configurable as eight differential outputs, 12 single-ended
outputs, or a combination of differential and single-ended
outputs.
The CY27410 has an on-chip volatile and nonvolatile memory,
composed of eight registers, which store the device
configuration settings. These registers can be accessed and
programmed onboard through the I
2
C interface. You can also
configure the device on-the-fly to completely reprogram the
device on the application board. Besides the I
2
C interface,
external signals can be applied to multifunction pins for different
functions such as the following:
■ Dynamically change the output frequency
■ Output enable/disable
■ Power down
■ Spread ON/OFF
One low-frequency clock output, in kilohertz, is provided to meet
the need of widely used reference frequencies, such as
32.768 kHz. The jitter specs of the CY27410 make it an ideal
choice for the following communication protocols: PCIe
1.0/2.0/3.0, USB 2.0/3.0, SATA 1.0/2.0, and 1/10GbE.
Input System
The input system supports the following (see Figure 1):
■ XIN/XOUT supports crystal input.
■ IN1 supports differential and single-ended clock inputs.
■ IN2 supports differential and single-ended clock inputs.
Figure 1. Oscillator/Clock Input Block Diagram
If a crystal is used, XIN and XOUT are connected to a crystal
oscillator to generate the required internal frequency, as shown
in Figure 2. The supported differential tuning capacitor range is
8 pF to 12 pF.
Figure 2. Connecting a Crystal
IN1 and IN2 are designed to accept either a single-ended or
differential reference input. IN2 can be used to accept the
feedback signal to implement the ZDB functionality of the device.
The differential inputs are capable of interfacing with multiple
standards, such as LVPECL, LVDS, CML, and HCSL. The
differential signals must be of AC-coupling, as shown in Figure 3.
Figure 3. Interfacing Differential and Single-Ended Signals
VCXO Input Block
The VIN input is used for the VCXO functionality of the device.
In this functionality, the output can change with respect to an
input voltage required for audio-visual applications. The output
frequency can vary up to ±120 ppm. This input voltage directly
controls the PLL 1 fractional divider to provide the VCXO
functionality.
Frequency Select Input
The CY27410 supports frequency-select features with which the
customer can change output frequencies on-the-fly. The device
has eight configuration register sets, which can be
preprogrammed or written through I
2
C. Changing the signal level
of the FS pins (high and low) selects the appropriate
configuration registers and changes the output frequency
accordingly.
MUX
DIV-R1
DIV-R2
IN1P
IN2P
XO
INC
INI
IN1S
IN2S
IN1N
IN2N
To Synthesis Section
XIN
XOUT
INxP
INxN
Termination
INxP
INxN
R
S
Differential Signal
LVCMOS Signal
100 pF
100 pF
