CY27410FLTXIT Datasheet CY27410FLTXI, CY27410FLTXIT | P7-P9

Document Number: 001-89074 Rev. *L Page 7 of 30

CY27410

Low-Frequency Output

The CY27410 integrates low-frequency generator counters for

LVCMOS outputs that may be used for watchdog-time and/or

kHz-order clocks for application, as shown in Figure 15.

Figure 15. Low-frequency Output Option

Spread Spectrum

To help reduce electromagnetic interference (EMI), the CY27410

supports spread-spectrum modulation. The output clock

frequencies can be modulated to spread energy across a

broader range of frequencies and lower system EMI. The

CY27410 implements two types of spread profiles for

modulation: linear and nonlinear.

The spread spectrum can be applied to any output clock, any

frequency, and any spread amount ranging from 0.1% to 5% in

0.1% steps. The center or down spread can be programmable.

The spread modulation rate is limited from 30 kHz to 60 kHz.

The spread spectrum is generated digitally in the FracN

modulation, which means all the parameters are independent of

process, voltage, and temperature variations. All the frequencies

generated by the same PLL have the same amount of

modulation.

As shown in Figure 16, a harmonic of a modulated clock has a

much lower amplitude than that of an unmodulated signal. The

reduction in amplitude is dependent on the harmonic number

and the frequency deviation or spread. The equation for the

reduction in the nonlinear profile is:

dB = 6.5 + 9 log

(P) + 9 * log

(F)

where P is the percentage of deviation and F is the frequency in

megahertz where the reduction is measured.

Figure 16. Spread-Spectrum Profile

VCXO (VCFS) Functionality

The CY27410 supports VCXO functionality without pulling the

crystal frequency. This function is implemented by modulating

the FracN counter according to the VIN level, as shown in

Figure 17. Therefore, this is called voltage-controlled frequency

shift (VCFS).

The VCFS function is implemented by modulating the FracN

divider, which means all the parameters are independent of the

process, voltage, and temperature variations.

It is not possible to combine the VCFS operation with spread

spectrum (see Figure 18).

Figure 17. VCFS Profile

Figure 18. VCFS and Spread Spectrum

DLY

FracN

PLL

Synthesis Block

Reference

Outputs

from Adjacent PLL

MAX

frequency

MAX

MIN

Frequency

Amplitude (dB)

EMI

Reduction

Typical Clock

SS Clock

Frequency

Amplitude (dB)

EMI

Reduction

Typical Clock

SS Clock

Frequency

Linear Profile

Nonlinear Profile

TimeTime

VIN

1/2 * VDD

Frequency

ppm

DLY

FracN

PLL

Synthesis Block

Reference

Outputs

from Adjacent PLL

SSC

VCFS

VIN

Document Number: 001-89074 Rev. *L Page 8 of 30

CY27410

Crystal Oscillator

The CY27410 supports various low-cost crystals as a reference

oscillator at IN1 (XIN/XOUT) to generate multiple frequencies in

a single chip. The CY27410 supports a crystal with a nominal

load capacitance specification from 8 pF to 12 pF. As shown in

Figure 2 on page 3, the CY27410 integrates all the components,

such as a feedback resistor and tuning capacitor, to oscillate the

clock with a particular crystal for the following specifications.

To enable proper operation, the crystal specification is divided

into three ranges:

■ Low range (F

NOM

) = 8 to 12 MHz

■ Midrange = 12 to 20 MHz

■ High range = 20 to 48 MHz

The corresponding crystal parameters are listed in Table 2.

Serial Programming Interface Protocol

The CY27410 uses the SDAT and SCLK pins for a 2-wire serial

interface that operates up to 400 Kb/s in Read and Write modes.

It complies with the I

C bus standard. The basic Write protocol is:

Start Bit; 7-bit Device Address; R/W Bit; Slave Clock

Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit

Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in

MA+2; ACK; and more until STOP Bit.

The basic serial format is shown in Figure 19.

Figure 19. Data Transfer Sequence on the Serial Bus

A valid write operation must have a full 8-bit register address

after the device address word from the master, which is followed

by an acknowledge bit from the slave (SDAT = 0/LOW). The next

eight bits must contain the data word intended for storage. After

the data word is received, the slave responds with another

acknowledge bit (SDAT = 0/LOW), and the master must end the

write sequence with a STOP condition (see Figure 20).

Figure 20. Data Frame Architecture (Write)

Table 2. Crystal Specifications

Range

Min

Frequency

(MHz)

Max

Frequency

(MHz)

Max R1

(ohms)

Max DL

(uW)

Low 8 12 150 100

Mid 12 20 70 100

High 20 48 50 100

(pF) for all Ranges Associated Max C

(pF)

8 2

9 2

10 2

12 3

SCLK

SDAT

START

Condition

Address or

Acknowledge

Valid

Data may

be changed

STOP

Condition

Write

Ack

Device Address

Start

Memory Address

Ack

Memory Data

Ack

Memory Data

Ack

Stop

Write

Ack

Device Address

Start

Memory Address

Ack

Memory Data

Ack

Stop

Random Write

Sequential Write

Document Number: 001-89074 Rev. *L Page 9 of 30

CY27410

Read operations are initiated the same way as write operations,

except that the R/W bit of the slave address is set to ‘1’ (HIGH).

There are two basic read operations: random read and

sequential read. Figure 21 illustrates these operations.

Figure 21. Data Frame Architecture (Read)

Through random read operations, the master may access any

memory location. To perform this type of read operation, first set

the word address. Send the address to the CY27410 as part of

a write operation. After the word address is sent, the master

generates a START condition following the acknowledge. This

terminates the write operation before any data is stored in the

address, but not before the internal address pointer is set. Next,

the master reissues the control byte with the R/W byte set to ‘1’.

Then, the CY27410 issues an acknowledge and transmits the

8-bit word. The master device does not acknowledge the

transfer, but does generate a STOP condition, which causes the

CY27410 to stop transmission.

Sequential read operations follow the same process as random

reads, except that the master issues an acknowledge instead of

a STOP condition after transmission of the first 8-bit data word.

This action results in an incrementing of the internal address

pointer, and subsequently output of the next 8-bit data word. By

continuing to issue acknowledges instead of STOP conditions,

the master may serially read the entire contents of the slave

device memory.

Write

Ack

Device Address

Start

Memory Address

Ack

Device Address

Start

Read

Memory Data

NAck

Stop

Write

Ack

Device Address

Start

Memory Address

Ack

Device Address

Start

Read

Memory Data

Ack

Memory Data

NAck

Stop

Random Read

Sequential Read

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

CY27410FLTXIT

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Clock Generators & Support Products 4PLL Spread-Spectrum Clock Generator

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CY27410FLTXIT

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