CY27410FLTXIT Datasheet CY27410FLTXI, CY27410FLTXIT | P4-P6

Document Number: 001-89074 Rev. *L Page 4 of 30

CY27410

C Block (SCLK, SDAT)

The CY27410 supports I

C programming of internal registers,

which can be used to configure the device. The CY27410 also

supports user-profile programming to flash memory and allows

partial updates. Read, Write, or Read/Write protection is also

available. The device is compliant with the I

C-bus Specification,

version 2.1 or later. The critical I

C specifications are as follows:

■ 400 kb/s (Fast mode)

■ 7-bit addressing support

■ Selectable device address (programmable), default = 69 hex

(7 bits)

Synthesis Section

The CY27410 contains four PLLs, which are the core synthesis

blocks of the chip. Each PLL has a fractional N capability, which

supports output frequency generation based on an input

reference frequency to an accuracy of 100 ppb. The output of the

PLL is fed into four dividers and then moves to synchronizers to

generate glitch-free clock transition features, variable delay

generation circuits to support the programmable delay feature,

and so on. The output dividers and multiplexers are also included

as part of this subsystem. All the four PLLs have the same

architecture, as shown in Figure 4.

Figure 4. PLL Architecture

Output Section

The CY27410 has two banks of outputs, which are located at the

top and bottom of the device. Each bank consists of six outputs

with OUT11–OUT14 and OUT21–OUT24 supporting both

differential and single-ended outputs and OUT15–OUT16 and

OUT25–OUT26 supporting only single-ended outputs.

Each output is fed from a PLL through a divider and then to a

MUX, which helps in selecting the source for the output, as

shown in Figure 5 and Figure 6.

Figure 5. Bank1 Outputs

Figure 6. Bank2 Outputs

INC

IN2S

PDET

Ox1

OUTC

DELAYDIVO1

DIVO2

DIVO3

DIVO4

P‐Path

FRAC

DIV N

SYNC

DIVCSYNC

IN1S

REF

FBK

DLY=0‐4cycles

Ox2

Ox3

Ox4

I‐Path

VCO

DIV2

SYNC

DIV2

DIV2SYNC

OUT11

DIFF/SE

OUT12

OUT13

OUT14

DIFF/SE

OUT15

OUT16

O11

O12

O13

O14

O21

O22

O23

DIV I

1/2/4/8

DIV I

1/2/4/8

MUX MUX MUX MUX MUX MUX

DIV L

O24

INI

OUT25

OUT26

OUT21

OUT22

OUT23

OUT24

DIFF/SE

O34

O33

O32

O31

O44

O43

O42

DIV I

1/2/4/8

DIV I

1/2/4/8

MUX MUX MUX MUX MUX MUX

DIV L

O41

INI

Document Number: 001-89074 Rev. *L Page 5 of 30

CY27410

Onboard Programming

One can write the device memory on the customer board,

enabling the use of a blank device that is not preprogrammed.

This enables use of the same device across multiple projects and

lets you program the device based on individual projects.

Conceptual onboard programming is shown in Figure 7.

Figure 7. Onboard Programming

Functional Features and Application Considerations

The CY27410 is a 4-PLL spread-spectrum clock generator

targeted at consumer, industrial, and low-end networking

applications. The key specifications of the part are differential

inputs (2) and outputs (12), supporting frequencies up to

700 MHz. The device has a low RMS phase jitter of 1-ps max

and value-added features, such as VCXO, Frequency Select,

and PLL Bypass modes. This part is designed to support key

standards, such as PCIe 1.0/2.0/3.0, USB 2.0/3.0, and 10GbE.

The product supports LVDS, LVPECL, CML, HCSL, and

LVCMOS logic levels.

Clock Generator

The main feature of the CY27410 is frequency generation from

an external reference (IN1) or a crystal. There are four variables

to determine the final output frequency. They are input REF, the

DIV-R (R1), FracN (DIV-N) dividers, and the post dividers

(DIV-O). The basic formula for determining the final output

frequency is:

■ Clock Generator mode

❐ f

OUT

= ((REF x DIV-N) / DIV-R) / DIV-O

■ PLL Bypass mode

❐ f

OUT

= REF / DIV-I or REF / DIV-I / DIV-L

The basic PLL block diagram is shown in Figure 8. Each of the

outputs from the PLL is fed to the output MUX through a Delay

circuit that provides a certain delay to the individual clock, if

needed.

Figure 8. PLL Block Diagram, Clock Generation

PCIE (HCSL) Clock Generation

For PCIe applications, the CY27410 provides eight differential

outputs that have the same spread on it at any particular point of

time.

VCXO and Related Frequencies

The CY27410 provides VCXO functionality and a cascading PLL

option to generate critical frequencies with a fixed reference.

Digital televisions have a requirement for the audio and video

clocks to follow a 27-MHz VCXO signal so that they are

synchronized. The architecture of the chip must ensure that this

is met by cascading, as shown in Figure 9.

Figure 9. Cascading PLLs

Apart from having the audio and video clocks following the

27-MHz VCXO input, they also need complex divider ratios to

generate the output frequencies. Commonly used divider ratios

for audio and video signals are listed in Tab l e 1.

Non Volatile

ControlStore

Volatile

ControlRegisters

POR, Initialize

I2C

OnBoard

Programming

Device

Configuration

Table 1. Audio and Video Frequencies

Output Frequency Ratios

74.17582418 91:250

33.8688 625:784

22.5792 1875:1568

16.9344 1250:784

11.2896 1875:784

5.6448 1875:392

36.864 375:512

DLY

FracN

PLL

Synthesis Block

Reference

Outputs

from Adjacent PLL

VCFS

(PLL1)

SS_PLL

PLL

XBUF

100MHzHCSL

66.66MHzLVCMOS

27MHzVCXO

VIDEO74.25MHz

AUDIO36.864MHz

REF

VIN

Document Number: 001-89074 Rev. *L Page 6 of 30

CY27410

Zero-Delay Buffer Functionality

The CY27410 acts as a zero-delay buffer (ZDB) for one output

from a single PLL block. To implement this feature, take one of

the outputs and send it back as a feedback reference to the PLL.

By providing a divider in the feedback loop, the device can also

act as a frequency-multiplying ZDB (see Figure 10). This

functionality is supported only when the PLL is in the integer N

mode.

Figure 10. ZDB Configuration

The CY27410 provides the frequency-multiplying ZDB by

modulating the R1 and R2 values in the integer ratio. If both the

values are identical, the CY27410 acts as a simple ZDB.

Early/Late Output Phase

The CY27410 supports a delay circuit in the divider to provide 0

to 4 × VCO/2 cycles. Therefore, an output has a certain lag

phase or lead phase to other outputs when this feature is used.

This functionality is also available in the ZDB mode and provides

“early” phase or “delayed” phase to the Reference input. Refer

to Figure 11 and Figure 12.

Figure 11. Early/Delayed Phase Output

Figure 12. Early/Late Phase in ZDB Configuration

Non-Zero Delay Buffer

The CY27410 supports the PLL-bypass mode, which bypasses

the entire synthesis block to act as a configurable non-zero delay

buffer (NZDB) with level translation and selectable inputs, as

shown in Figure 13.

Figure 13. NZDB Configuration

Combination Clock Generator and Buffer

The CY27410 provides a combination of a clock generator and

a buffer in one device. This is achieved by configuring the input

and output selectors for the desired split configuration. An

example of such an application is shown in Figure 14.

Figure 14. Clock Generator and NZDB

DLY

FracN

PLL

Synthesis Block

Reference

Outputs

from Adjacent PLL

REF

DLY

FracN

PLL

Synthesis Block

Reference

Outputs

from Adjacent PLL

DLY

FracN

PLL

Synthesis Block

Reference

Outputs

from Adjacent PLL

DLY

FracN

PLL

Synthesis Block

Reference

Outputs

from Adjacent PLL

DLY

FracN

PLL

Synthesis Block

Reference

Outputs

from Adjacent PLL

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CY27410FLTXIT

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Buy CY27410FLTXIT

Manufacturer:

Cypress Semiconductor

Description:

Clock Generators & Support Products 4PLL Spread-Spectrum Clock Generator

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CY27410FLTXIT

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