Document Number: 001-89074 Rev. *L Page 22 of 30
CY27410
Table 19. Spread-Spectrum Specifications
Symbol Description Conditions Min Typ Max Units
F
MOD
Modulation rate 30 60 kHz
SSper Spread spectrum amount Tota l % 0.1 5.0 %
SSStep Spread spectrum% step 0.1 %
Table 20. Output Selection Specifications
Symbol Description Conditions Min Typ Max Units
t
FS
Frequency switching time Frequency switching time for
OUT13,14, 23, 24. Both PLLs are
active (change MUX selection Bit).
500 µs
t
FS
Frequency switching time Frequency switching time for all
outputs, DIVO value change
500 µs
t
FS
Frequency switching time Frequency switching time for all
outputs. PLL value change.
1000 µs
t
FS
Output turn-on time Output turn-on time from FS. PLL is
active, change OE or MUX.
500 µs
t
FS
Output turn-on time Output turn-on time from FS. Resume
PLL from Power Down.
1000 µs
t
OFF
Output turn-off time Output turn-off time from FS. PLL is
active, change OE or MUX.
500 µs
Table 21. NV Memory Specification
Symbol Description Conditions Min Typ Max Units
DRET NV memory data retention 10 Years
PROG
CYCLE
Programming cycle Programming cycle for NV memory 100 K Cycle
Table 22. Miscellaneous Specifications
Symbol Description Conditions Min Typ Max Units
t
XRES
XRES Low time 10 µs
T
PROG
Flash programming temperature 5 55 °C
C
INADC
Input capacitance VIN pin 10 pF
Note
4. These parameters are guaranteed by design and are not tested.
Table 23. Thermal Resistance
Parameter
[4]
Description Test Conditions 48-pin QFN Unit
θ
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
15.64 °C/W
θ
JC
Thermal resistance
(junction to case)
2.21 °C/W
Document Number: 001-89074 Rev. *L Page 23 of 30
CY27410
Test and Measurement Circuits
Figure 23. LVPECL Output Load and Test Circuit Figure 24. LVDS Output Load and Test Circuit
Figure 25. CML Output Load and Test Circuit Figure 26. HCSL Output Load and Test Circuit
Figure 27. LVCMOS Output Load and Test Circuit
TP
TP
V
DDIO
– 2 V
BUF
50 50
V
DDIO
50
50
TP
TP
BUF
100
V
DDIO
50
50
TP
TP
V
DDIO
BUF
50
50
50
V
DDIO
50
TP
TP
BUF
33
33
V
DDIO
49.9 49.9
5”
2 pF
2 pF
50
50
TP
BUF
V
DDIO
C
LOAD
Document Number: 001-89074 Rev. *L Page 24 of 30
CY27410
Voltage and Timing Definitions
Figure 28. LVCMOS Input Definitions Figure 29. LVCMOS Output Definitions
Figure 30. Differential Input Definitions Figure 31. Differential Output Definitions
Figure 32. Skew Definition Figure 33. Propagation Delay Definition
Figure 34. Output Enable/Disable/Frequency Select Timing Figure 35. HCSL Single-ended Measurement Point-2
Figure 36. HCSL Differential Measurement Point Figure 37. HCSL Differential Measurement for Ringback
50% of V
DD
Clock
20% of V
DD
80% of V
DD
t1 t2
t
R
t
F
t
DC
= t1 / (t1 + t2)
V
IH
V
IL
50% of V
IOX
OUT
20% of V
IOX
80% of V
IOX
t1 t2
t
R
t
F
t
ODC
= t1 / (t1 + t2)
V
OH
V
OL
t
PW
t
PERIOD
V
PP
ID
Clock-P
Clock-N
V
A
V
B
V
OCM
= (V
A
+ V
B
) / 2
t
DC
= t
PW
/ t
PERIOD
t
PW
t
PERIOD
V
PP
OUT-P
OUT-N
V
A
V
B
V
OCM
= (V
A
+ V
B
) / 2
t
DC
= t
PW
/ t
PERIOD
80%
20%
80%
20%
t
F
t
R
t
SK1
OUTx
OUTy
OUTx
OUTy
50% of V
IOX
50% of V
IOX
V
OCM
V
OCM
t
PD
INx
OUTy
INx
OUTy
50% of V
IOX
50% of V
IOX
V
OCM
V
OCM
FS
CLOCK
OriginalClock NewClock
t
OFF
t
FS
Rise and Fall Time Matching
V
CROSSMEDIAN
OUTN
OUTP
V
CROSSMEDIAN
+75mV
V
CROSSMEDIAN
‐75mV
V
CROSSMEDIAN
OUTN
OUTP
T
FALL
T
RISE
Duty Cycle and Period
ClockPeriod(Differential)
PositiveDuty
Cycle(Differential)
NegativeDuty
Cycle(Differential)
0.0V
OUTP+
OUTN
V
IH
=+150mV
V
RB
=+100mV
V
RB
=‐100mV
V
IL
=‐150mV
OUTP+
OUTN
T
STABLE
T
STABLE
V
RB
V
RB

CY27410FLTXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Clock Generators & Support Products 4PLL Spread-Spectrum Clock Generator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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