Document Number: 001-89074 Rev. *L Page 14 of 30
DC Chip-Level Specifications
t
PLLLOCK
PLL lock time Time from PLL enabled to PLL stable (PLL
reaches at ±1-ppm accuracy)
– – 250 s
t
LOCK
Device power-up time Time from minimum specified V
DD
to Output
Stable in XO-based clock gen mode. In the
case of external clock input, t
LOCK
will reduce
by the crystal oscillator startup time
(t
OSCSTART
). This specification is valid when
the reference is available and stable at
startup.
For supply ramps slower than the t
PU_SR
spec where customers use XRES during
power up. Power-up time will be calculated
from the release of XRES to output stable.
– – 10.0 ms
t
OSCSTART
Crystal oscillator startup time Time from crystal oscillator power-up to
crystal oscillator stable. Crystal FNOM =
25 MHz, C1>1 fF
– – 4 ms
t
PU_SR
Power supply slew rate during
power up
Power-supply ramp rate for V
DD
to reach
minimum specified voltage (power ramp
must be monotonic). For supply ramps
slower than 1 V/ms, use XRES to externally
keep the part in RESET during power-up and
release XRES after V
DD
reaches the
minimum specification.
1 – 67 V/ms
Table 7. DC Electrical Specifications Input
Symbol Description Conditions Min Typ Max Units
V
IH33
Input high voltage LVCMOS and logic inputs, V
DD
= 3.3 V 2.0 – – V
V
IH25
Input high voltage LVCMOS and logic inputs, V
DD
= 2.5 V 1.7 – – V
V
IH18
Input high voltage LVCMOS and logic inputs, V
DD
= 1.8 V 1.1 – – V
V
IL33
Input low voltage LVCMOS and logic inputs, V
DD
= 3.3 V – – 0.8 V
V
IL25
Input low voltage LVCMOS and logic inputs, V
DD
= 2.5 V – – 0.7 V
V
IL18
Input low voltage LVCMOS and logic inputs, V
DD
= 1.8 V – – 0.5 V
V
DIFF
Differential input LVDS, CML, PECL, HCSL. Differential
amplitude, pk.
0.30 – 1.45 V
DC
DIFF
Duty cycle, differential clock input Measured at crossing point 40 50 60 %
DC
LVCMOS
Duty cycle, LVCMOS clock input Measured at 1/2 V
DD
40 50 60 %
I
IH
Input high current Input = V
DD
– – 150 A
I
IL
Input low current Input = GND –150 – – A
C
IN
Input capacitance, IN1, IN2 Measured at 10 MHz, differential – – 3.0 pF
V
PPSINE
AC input swing pk Clipped sine wave, AC coupled through a
1000-pF capacitor.
0.8 1.0 1.2 V
R
P
Input pull-down resistance LVCMOS clock input 75 115 170 k
Table 6. Operating Power Supply (continued)
Symbol Description Conditions Min Typ Max Units
