Document Number: 001-89074 Rev. *L Page 16 of 30
AC Input Clock Specifications
AC Output Specifications
Table 12. DC Specifications for HCSL Output (V
DDIO
= 2.5-V or 3.3-V range)
Symbol Description Conditions Min Typ Max Units
V
OCM
Output common mode voltage Common mode 350 –400mV
V
OHDIFF
Differential output high voltage Measurement taken from differential
waveform
150 ––mV
V
OLDIFF
Differential output low voltage Measurement taken from differential
waveform
– – –150 mV
V
CROSS
Absolute crossing point voltage Measurement taken from single-ended
waveform
250 –550mV
V
CROSSDELTA
Variation of V
CROSS
over all
rising clock edges
Measurement taken from single-ended
waveform
– –140mV
Table 13. Input Frequency Range
Symbol Description Conditions Min Typ Max Units
F
CRYSTAL
Crystal frequency Fundamental AT CUT crystal 8 – 48 MHz
F
REFERENCE
Reference frequency Internal reference to PLL 8 – 40 MHz
F
INCMOS
LVCMOS input frequency Buffer mode, all PLLs OFF 8 – 250 MHz
F
INCMOS
LVCMOS input frequency Buffer mode, one or more PLL active 8 – 125 MHz
F
INCMOS
LVCMOS input frequency CLKGEN mode 8 – 250 MHz
F
INCMOS
LVCMOS input frequency ZDB mode, PLL in integer N configuration 8 – 250 MHz
F
INDIFF
Differential clock input frequency Buffer mode, all PLLs OFF 8 – 700 MHz
F
INDIFF
Differential clock input frequency Buffer mode, one or more PLL active 8 – 125 MHz
F
INDIFF
Differential clock input frequency CLKGEN mode 8 – 300 MHz
F
INDIFF
Differential clock input frequency ZDB mode, PLL in integer N configuration 8 – 300 MHz
F
INCAS
Cascading clock frequency Internal cascading frequency in the Buffer
mode
8 – 125 MHz
Table 14. AC Input Clock Electrical Specification
Symbol Description Conditions Min Typ Max Units
t
CMOSDC
LVCMOS clock input duty cycle Measured at 1/2 V
DD
20%–80%, Functional 40 50 60 %
t
DIFFDC
Differential clock input duty cycle Measured at V
OCM
20%–80%, Functional 40 50 60
t
RFCMOS
LVCMOS clock input rise/fall
time
Measured between 20%–80% of V
DD
––4ns
Table 15. AC Electrical Specifications LVCMOS Output. Load: 15 pF < 100MHz, 7.5 pF < 200 MHz, 5 pF > 200 MHz
Symbol Description Conditions Min Typ Max Units
Common AC Electrical Specifications
t
RFCMOS
Rise/fall time f
OUT
< 100MHz, 20%–80% – – 2.0 ns
t
RFCMOS
Rise/fall time f
OUT
< 200MHz, 20%–80% – – 1.5 ns
t
RFCMOS
Rise/fall time f
OUT
< 250MHz, 20%–80% – – 1.3 ns
t
SKEW
Output to output skew Equally loaded, measured at 1/2 V
IOX
, in a
bank, derived from the same PLL,
– – 150 ps
Buffer Mode
f
OUT
Output frequency All PLLs off 8 250 MHz
