Data Sheet AD7152/AD7153
Rev. A | Page 13 of 24
REGISTER MAP
The master can write to or read from all of the registers except
the address pointer register, which is a write-only register. The
address pointer register determines which register the next read
or write operation accesses. All communications with the device
through the bus start with an access to the address pointer
register. After the device has been accessed over the bus and a
read/write operation is selected, the address pointer register is
set up. The address pointer register determines from or to which
register the operation takes place. A read/write operation is
performed from/to the target address, which then increments to
the next address until a stop command on the bus is performed.
Table 6. Register Summary
Register Name
Subaddress
Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default
Value
Dec
Hex
Status 0 0x00 R PWDN Unused Unused Unused Unused C1C2
RDY2
RDY1
0x03
Channel 1 Data MSB 1 0x01 R Channel 1 data, high byte 0x00
Channel 1 Data LSB 2 0x02 R Channel 1 data, low byte 0x00
Channel 2 Data MSB
1
3 0x03 R Channel 2 data, high byte 0x00
Channel 2 Data LSB 4 0x04 R Channel 2 data, low byte 0x00
Channel 1 Offset MSB 5 0x05 R/W Channel 1 offset calibration coefficient, high byte 0x80
Channel 1 Offset LSB 6 0x06 R/W Channel 1 offset calibration coefficient, low byte 0x00
Channel 2 Offset MSB
1
7 0x07 R/W Channel 2 offset calibration coefficient, high byte 0x80
Channel 2 Offset LSB
1
8 0x08 R/W Channel 2 offset calibration coefficient, low byte 0x00
Channel 1 Gain MSB 9 0x09 R/W Channel 1 gain coefficient, high byte, factory calibrated 0xXX
Channel 1 Gain LSB 10 0x0A R/W Channel 1 gain coefficient, low byte, factory calibrated 0xXX
Channel 1 Setup 11 0x0B R/W Range 1 Range 0 CAPDIFF Unused Unused 0x00
Channel 2 Gain MSB
1
12 0x0C R/W Channel 2 gain coefficient, high byte, factory calibrated 0xXX
Channel 2 Gain LSB
1
13
0x0D
R/W
Channel 2 gain coefficient, low byte, factory calibrated
0xXX
Channel 2 Setup
1
14 0x0E R/W Range 1 Range 0 CAPDIFF Unused Unused 0x00
Configuration 15 0x0F R/W Unused Unused Unused Ch1en Ch2en MD2 MD1 MD0 0x00
Reserved 16 0x10 R/W Unused 0x00
CAPDAC POS 17 0x11 R/W DACPen Unused Unused DACP Bits[4:0] value 0x00
CAPDAC NEG 18 0x12 R/W DACNen Unused Unused DACN Bits[4:0] value 0x00
Configuration2 26 0x1A R/W Unused Unused OSR1 OSR0 Unused Unused Unused Unused 0x00
1
AD7152 only.
AD7152/AD7153 Data Sheet
Rev. A | Page 14 of 24
STATUS REGISTER
Address 0x00
Read Only
Default Value 0x03
This register indicates the status of the converter. The status register can be read via the 2-wire serial interface to query a finished
conversion.
Table 7. Status Register Bit Map
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic PWDN Unused Unused Unused Unused C1C2
RDY2 RDY1
Default 0 0 0 0 0 0 1 1
Table 8. Status Register Bit Descriptions
Bit Mnemonic Description
7 PWDN PWDN = 1 indicates that the V
DD
voltage level is below 2.45 V typically or the device is in power-down mode
6 to 3 N/A Not used, always read 0
2
C1C2
C1C2 = 0 indicates that the last conversion performed was from Channel 1, C1C2 = 1 indicates that the last
conversion performed was from Channel 2
1
RDY2 RDY2 = 0 indicates that a conversion on the Channel 2 has been finished and new unread data is available (AD7152 only)
0
RDY1 RDY1 = 0 indicates that a conversion on the Channel 1 has been finished and new unread data is available
Data Sheet AD7152/AD7153
Rev. A | Page 15 of 24
DATA REGISTERS
Address 0x01, Address 0x02 for Channel 1,
Address 0x03, Address 0x04 (AD7152 Only) for Channel 2,
16 Bits, Read-Only, Default Value 0x0000
Data from the last complete capacitance-to-digital conversion
reflects the capacitance on the input. Only the 12 MSBs of the
data registers are used for the CDC result. The 4 LSBs are
always 0, as shown in Figure 24.
BIT 7
BIT 6 BIT 5
BIT 4 BIT 3 BIT 2
12-BIT CDC RESULT
BIT 1 BIT 0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
DATA HIGHMSB DATA LOW LSB
BIT 1
BIT 0
0
07450-044
Figure 24. CDC Data Register
The AD7152/AD7153 are factory gain calibrated and map the
CDC full-scale raw data range of 0x3000 to 0xCFF0 to a CDC
full-scale data register range of 0x0000 to 0xFFF0 (see Table 9).
Table 9. AD7152/AD7153 Capacitance-to-Data Mapping
Data Reg
Input Capacitance (4 pF range)
Differential Mode Single-Ended Mode
0x0000
Negative full scale (2 pF)
Zero scale (0 pF)
0x8000 Zero scale (0 pF) Midscale (2 pF)
0xFFF0 Positive full scale (+2 pF) Full scale (4 pF)
The data register output in differential mode is internally
calculated using the following equation:
Data Reg = (Code – (Offset Reg0x8000)) × Gain + 0x8000 (1)
The input capacitance can be calculated from the output data
using the following equation:
RangeInput
xRegData
C ×
=
0xFFF0
80000
(pF)
(2)
The data register output in single-ended mode is internally
calculated using the following equation:
Data Reg = (Code − (Offset Reg 0x3000)) × Gain (3)
The input capacitance can be calculated from the output data
using the following equation:
RangeInput
RegData
C ×=
0
xFFF0
(pF)
(4)
where Input Range = 4 pF, 2 pF, 1 pF, or 0.5 pF.
A data register is updated after a finished conversion on the
capacitive channel, with one exception: when the serial interface
read operation from the data register is in progress, the data
register is not updated and the new capacitance conversion
result is lost.
The stop condition on the serial interface is considered to be the
end of the read operation.
Therefore, to prevent incorrect data reading through the
serial interface, the two bytes of a data register should be
read sequentially using the register address pointer auto-
increment feature of the serial interface.
OFFSET CALIBRATION REGISTERS
Address 0x05, Address 0x06 for Channel 1,
Address 0x07, Address 0x08 for Channel 2 (AD7152 Only)
16 Bits Read/Write, Default Value 0x8000
The offset calibration registers hold the zero-scale calibration
coefficients.
The zero-scale calibration coefficient digitally maps the zero
capacitance on the CDC input to the zero-scale data code.
The coefficient can be used for compensation of the AD7152/
AD7153 internal offset as well as the system level offset within
specified offset calibration limits.
Users can set the coefficient by executing the offset calibration
after connecting the zero-scale capacitance to the system input.
Alternatively, the coefficient value can be written to the offset
calibration register(s) by the host software, for example, values
stored in a host nonvolatile memory.
Note that there is a difference between code mapping in differ-
ential and single-ended input mode. In differential mode, the
nominal zero-scale calibration coefficient value is a power-on
default, 0x8000. In singleended mode, the nominal zero-scale
calibration coefficient value is 0x3000.
The difference means that before using the single-ended mode
(or any time when changing between modes afterwards), the
user should either perform offset calibration with capacitance
close to 0 pF connected to the input or write the offset calibra-
tion register(s) value(s) close to 0x8000 for differential mode or
value close to 0x3000 for single-ended mode.
On the AD7152, the two capacitive channels have individual
offset registers and each channel can be calibrated individually.
GAIN CALIBRATION REGISTERS
Address 0x09, Address 0x0A for Channel 1
Address 0x0C, Address 0x0D for Channel 2 (AD7152 Only)
16 Bits Read/Write, Default Value 0xXXXX
The capacitive gain calibration registers hold the capacitive
channel full-scale factory calibration coefficient. The gain
calibration factor can be calculated using the following
equation:
16
16
2
2 RegGain
Gain
+
=
(5)
On the AD7152, the two capacitive channels each have a gain
register, which allows the device to gain calibrate each channel
individually.

AD7153BRMZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 1-CH 12-bit CDC IC
Lifecycle:
New from this manufacturer.
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