Table 6. Control timing (continued)
Num C Rating Symbol Min Typical
1
Max Unit
C Port rise and fall time -
high drive strength (load =
50 pF)
5
— t
Rise
— 5.4 — ns
C t
Fall
— 4.6 — ns
1. Typical values are based on characterization data at V
DD
= 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of t
MSH
after
V
DD
rises above V
LVD
.
4. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5. Timing is shown with respect to 20% V
DD
and 80% V
DD
levels in operating temperature range.
t
extrst
RESET PIN
Figure 9. Reset timing
t
IHIL
KBIPx
t
ILIH
IRQ/KBIPx
Figure 10. IRQ/KBIPx timing
5.2.2
Debug trace timing specifications
Table 7. Debug trace operating behaviors
Symbol Description Min. Max. Unit
t
cyc
Clock period Frequency dependent MHz
t
wl
Low pulse width 2 — ns
t
wh
High pulse width 2 — ns
t
r
Clock and data rise time — 3 ns
t
f
Clock and data fall time — 3 ns
t
s
Data setup 3 — ns
t
h
Data hold 2 — ns
Switching specifications
MC9S08PA4 Data Sheet, Rev. 8, 08/2018
16 NXP Semiconductors
