Table 15. Pin availability by package pin-count
Pin Number Lowest Priority <-- --> Highest
20-SOIC/
TSSOP
16-TSSOP 8-DFN/SOIC Port Pin Alt 1 Alt 2 Alt 3 Alt 4
1 1 1 PTA5 IRQ FTM1CH0 — RESET
2 2 2 PTA4 — ACMPO BKGD MS
3 3 3 — — — — V
DD
4 4 4 — — — — V
SS
5 5 — PTB7 — — — EXTAL
6 6 — PTB6 — — — XTAL
7 7 — PTB5
1
— FTM1CH1 — —
8 8 — PTB4
1
— FTM1CH0 — —
9 — — PTC3 — — — —
10 — — PTC2 — — — —
11 — — PTC1 — — — —
12 — — PTC0 — — — —
13 9 — PTB3 KBI0P7 — TCLK1 ADP7
14 10 — PTB2 KBI0P6 — — ADP6
15 11 — PTB1 KBI0P5 TxD0 — ADP5
16 12 — PTB0
2
KBI0P4 RxD0 TCLK0 ADP4
17 13 5 PTA3 KBI0P3 FTM0CH1 TxD0 ADP3
18 14 6 PTA2 KBI0P2 FTM0CH0 RxD0 ADP2
19 15 7 PTA1 KBI0P1 FTM0CH1 ACMP1 ADP1
20 16 8 PTA0 KBI0P0 FTM0CH0 ACMP0 ADP0
1. This is a high current drive pin when operated as output.
2. This is a true open-drain pin when operated as output.
Note
When an alternative function is first enabled, it is possible to
get a spurious edge to the module. User software must clear any
associated flags before interrupts are enabled. The table above
illustrates the priority if multiple modules are enabled. The
highest priority module will have control over the pin. Selecting
a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority
module. Disable all modules that share a pin before enabling
another module.
8.2
Device pin assignment
Pinout
MC9S08PA4 Data Sheet, Rev. 8, 08/2018
26 NXP Semiconductors
