1. Maximum T
A
can be exceeded only if the user ensures that T
J
does not exceed the maximum. The simplest method to
determine T
J
is: T
J
= T
A
+ R
θJA
x chip power dissipation.
6 Peripheral operating requirements and behaviors
6.1 External oscillator (XOSC) and ICS characteristics
Table 10. XOSC and ICS specifications in operating temperature range
Num C Characteristic Symbol Min Typical
1
Max Unit
1 C Oscillator
crystal or
resonator
Low range (RANGE = 0) f
lo
31.25 32.768 39.0625 kHz
C High range (RANGE = 1)
FEE or FBE mode
2
f
hi
4 20 MHz
C High range (RANGE = 1),
high gain (HGO = 1),
FBELP mode
f
hi
4 20 MHz
C High range (RANGE = 1),
low power (HGO = 0),
FBELP mode
f
hi
4 20 MHz
2 D Load capacitors C1, C2 See Note
3
3 D Feedback
resistor
Low Frequency, Low-Power
Mode
4
R
F
MΩ
Low Frequency, High-Gain
Mode
10 MΩ
High Frequency, Low-
Power Mode
1 MΩ
High Frequency, High-Gain
Mode
1 MΩ
4 D Series resistor -
Low Frequency
Low-Power Mode
4
R
S
kΩ
High-Gain Mode 200 kΩ
5 D Series resistor -
High Frequency
Low-Power Mode
4
R
S
kΩ
D Series resistor -
High
Frequency,
High-Gain Mode
4 MHz 0 kΩ
D 8 MHz 0 kΩ
D 16 MHz 0 kΩ
6 C Crystal start-up
time Low range
= 32.768 kHz
crystal; High
range = 20 MHz
crystal
5
,
6
Low range, low power t
CSTL
1000 ms
C Low range, high power 800 ms
C High range, low power t
CSTH
3 ms
C High range, high power 1.5 ms
7 T Internal reference start-up time t
IRST
20 50 µs
8 D Square wave
input clock
frequency
FEE or FBE mode
2
f
extal
0.03125 5 MHz
D FBELP mode 0 20 MHz
Table continues on the next page...
Peripheral operating requirements and behaviors
MC9S08PA4 Data Sheet, Rev. 8, 08/2018
NXP Semiconductors 19
Table 10. XOSC and ICS specifications in operating temperature range (continued)
Num C Characteristic Symbol Min Typical
1
Max Unit
9 P Average internal reference frequency -
trimmed
f
int_t
31.25 kHz
10 P DCO output frequency range - trimmed f
dco_t
16 20 MHz
11 P Total deviation
of DCO output
from trimmed
frequency
5
Over full voltage and
temperature range
Δf
dco_t
±2.0 %f
dco
C Over fixed voltage and
temperature range of 0 to
70 °C
±1.0
12 C FLL acquisition time
5
,
7
t
Acquire
2 ms
13 C Long term jitter of DCO output clock
(averaged over 2 ms interval)
8
C
Jitter
0.02 0.2 %f
dco
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25
kHz to 39.0625 kHz.
3. See crystal or resonator manufacturer's recommendation.
4. Load capacitors (C
1
,C
2
), feedback resistor (R
F
) and series resistor (R
S
) are incorporated internally when RANGE = HGO =
0.
5. This parameter is characterized and not tested on each device.
6. Proper PC board layout procedures must be followed to achieve specifications.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V
DD
and V
SS
and variation in crystal oscillator frequency increase the C
Jitter
percentage
for a given interval.
XOSC
EXTAL XTAL
Crystal or Resonator
R
S
C
2
R
F
C
1
Figure 15. Typical crystal or resonator circuit
Peripheral operating requirements and behaviors
MC9S08PA4 Data Sheet, Rev. 8, 08/2018
20 NXP Semiconductors
6.2 NVM specifications
This section provides details about program/erase times and program/erase endurance for
the flash and EEPROM memories.
Table 11. Flash characteristics
C Characteristic Symbol Min
1
Typical
2
Max
3
Unit
4
D Supply voltage for program/erase in the
operating temperature range
V
prog/erase
2.7 5.5 V
D Supply voltage for read operation V
Read
2.7 5.5 V
D NVM Bus frequency f
NVMBUS
1 25 MHz
D NVM Operating frequency f
NVMOP
0.8 1 1.05 MHz
D Erase Verify All Blocks t
VFYALL
17338 t
cyc
D Erase Verify Flash Block t
RD1BLK
16913 t
cyc
D Erase Verify EEPROM Block t
RD1BLK
810 t
cyc
D Erase Verify Flash Section t
RD1SEC
484 t
cyc
D Erase Verify EEPROM Section t
DRD1SEC
555 t
cyc
D Read Once t
RDONCE
450 t
cyc
D Program Flash (2 word) t
PGM2
0.12 0.12 0.29 ms
D Program Flash (4 word) t
PGM4
0.20 0.21 0.46 ms
D Program Once t
PGMONCE
0.20 0.21 0.21 ms
D Program EEPROM (1 Byte) t
DPGM1
0.10 0.10 0.27 ms
D Program EEPROM (2 Byte) t
DPGM2
0.17 0.18 0.43 ms
D Program EEPROM (3 Byte) t
DPGM3
0.25 0.26 0.60 ms
D Program EEPROM (4 Byte) t
DPGM4
0.32 0.33 0.77 ms
D Erase All Blocks t
ERSALL
96.01 100.78 101.49 ms
D Erase Flash Block t
ERSBLK
95.98 100.75 101.44 ms
D Erase Flash Sector t
ERSPG
19.10 20.05 20.08 ms
D Erase EEPROM Sector t
DERSPG
4.81 5.05 20.57 ms
D Unsecure Flash t
UNSECU
96.01 100.78 101.48 ms
D Verify Backdoor Access Key t
VFYKEY
464 t
cyc
D Set User Margin Level t
MLOADU
407 t
cyc
C FLASH Program/erase endurance T
L
to
T
H
in the operating temperature range
n
FLPE
10 k 100 k Cycles
C EEPROM Program/erase endurance TL
to TH in the operating temperature
range
n
FLPE
50 k 500 k Cycles
C Data retention at an average junction
temperature of T
Javg
= 85°C after up to
10,000 program/erase cycles
t
D_ret
15 100 years
1. Minimum times are based on maximum f
NVMOP
and maximum f
NVMBUS
2. Typical times are based on typical f
NVMOP
and maximum f
NVMBUS
3. Maximum times are based on typical f
NVMOP
and typical f
NVMBUS
plus aging
4. t
cyc
= 1 / f
NVMBUS
Peripheral operating requirements and behaviors
MC9S08PA4 Data Sheet, Rev. 8, 08/2018
NXP Semiconductors 21

MC9S08PA4VWJ

Mfr. #:
Manufacturer:
NXP / Freescale
Description:
8-bit Microcontrollers - MCU 8 BIT,low end Core,4k Fl
Lifecycle:
New from this manufacturer.
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