Rev. 1.6 19
Si8650/51/52/55
2.2. Eye Diagram
Figure 7 illustrates an eye-diagram taken on an Si8650. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8650 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited.
Figure 7. Eye Diagram
20 Rev. 1.6
Si8650/51/52/55
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 8, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present. Additionally, refer to Table 13 for logic conditions when enable pins are used.
Table 12. Si865x Logic Operation
V
I
Input
1,2
EN
Input
1,2,3,4
VDDI
State
1,5,6
VDDO
State
1,5,6
V
O
Output
1,2
Comments
H H or NC P P H Enabled, normal operation.
LH or NC P P L
X
7
L P P Hi-Z
8
Disabled.
X
7
H or NC UP P
L
9
H
9
Upon transition of VDDI from unpowered to pow-
ered, V
O
returns to the same state as V
I
in less
than 1 µs.
X
7
L UP P Hi-Z
8
Disabled.
X
7
X
7
P UP Undetermined Upon transition of VDDO from unpowered to pow-
ered, V
O
returns to the same state as V
I
within
1 µs, if EN is in either the H or NC state. Upon tran-
sition of VDDO from unpowered to powered, V
O
returns to Hi-Z within 1 µs if EN is L.
Notes:
1. VDDI and VDDO are the input and output power supplies. V
I
and V
O
are the respective input and output terminals. EN
is the enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si865x is
operating in noisy environments.
4. No Connect (NC) replaces EN1 on Si8650. No Connects are not internally connected and can be left floating, tied to
VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is
disabled (EN = 0).
9. See "6. Ordering Guide" on page 28 for details. This is the selectable fail-safe operating mode (ordering option). Some
devices have default output state = H, and some have default output state = L, depending on the ordering part number
(OPN). For default high devices, the data channels have pull-ups on inputs/outputs. For default low devices, the data
channels have pull-downs on inputs/outputs.
Rev. 1.6 21
Si8650/51/52/55
Table 13. Enable Input Truth
1
P/N
EN1
1,2
EN2
1,2
Operation
Si8650 H Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
L Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance
state.
3
Si8651 H X Output A5 enabled and follow input state.
L X Output A5 disabled and in high impedance state.
3
X H Outputs B1, B2, B3, B4 are enabled and follow input state.
X L Outputs B1, B2, B3, B4 are disabled and in high impedance state.
3
Si8652 H X Outputs A4 and A5 are enabled and follow input state.
L X Outputs A4 and A5 are disabled and in high impedance state.
3
X H Outputs B1, B2, B3 are enabled and follow input state.
X L Outputs B1, B2, B3 are disabled and in high impedance state.
3
Si8655 Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
Notes:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are
internally pulled-up to local VDD by a 2 µA current source allowing them to be connected to an external logic level (high
or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If
EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si865x is
operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is
disabled (EN = 0).

SI8650BC-B-IS1R

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Digital Isolators 3.75 kV 5-channel digital isolator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet