34 Rev. 1.6
Si8650/51/52/55
10. Land Pattern: 16-Pin Narrow Body SOIC
Figure 19 illustrates the recommended land pattern details for the Si865x in a 16-pin narrow-body SOIC. Table 18
lists the values for the dimensions shown in the illustration.
Figure 19. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 18. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 5.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.6 35
Si8650/51/52/55
11. Package Outline: 16-Pin QSOP
Figure 20 illustrates the package details for the Si865x in a 16-pin QSOP package. Table 19 lists the values for the
dimensions shown in the illustration.
Figure 20. 16-pin QSOP Package
36 Rev. 1.6
Si8650/51/52/55
Table 19. Package Diagram Dimensions
Dimension Min Max
A 1.75
A1 0.10 0.25
A2 1.25
b 0.20 0.30
c 0.17 0.25
D 4.89 BSC
E 6.00 BSC
E1 3.90 BSC
e 0.635 BSC
L 0.40 1.27
L2 0.25 BSC
h 0.25 0.50
θ
aaa 0.10
bbb 0.20
ccc 0.10
ddd 0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.

SI8650BC-B-IS1R

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Digital Isolators 3.75 kV 5-channel digital isolator
Lifecycle:
New from this manufacturer.
Delivery:
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