19©2017 Integrated Device Technology, Inc. October 24, 2017
5L2503 Datasheet
Byte 15: Output Divider1 Control
Byte 16: PLL2 Integer Feedback Divide
Byte 17: PLL2 Integer Feedback Divider
Byte 0Fh Name Control Function Type 0 1 PWD
Bit 7 OUTDIV1[3] Output divider1 control bit 3 R/W
DIV1[3:2] = 1,2,4,8; DIV1[1:0] =
1,4,5,6; Default Divider = 1 x 1 = 1
0
Bit 6 OUTDIV1[2] Output divider1 control bit 2 R/W 0
Bit 5 OUTDIV1[1] Output divider1 control bit 1 R/W 0
Bit 4 OUTDIV1[0] Output divider1 control bit 0 R/W 0
Bit 3 OUTDIV2[3] Output divider2 control bit 3 R/W
DIV2[3:2] = 1,2,4,5; DIV2[1:0] =
1,3,5,10; Default Divider = 1 x 10 =
10
0
Bit 2 OUTDIV2[2] Output divider2 control bit 2 R/W 0
Bit 1 OUTDIV2[1] Output divider2 control bit 1 R/W 1
Bit 0 OUTDIV2[0] Output divider2 control bit 0 R/W 1
Byte 10h Name Control Function Type 0 1 PWD
Bit 7 Reserved 0
Bit 6 Reserved 0
Bit 5 Reserved 0
Bit 4 Reserved 0
Bit 3 Reserved 0
Bit 2 PLL2_FB_INT[10] PLL2 feedback integer divider 10 R/W 0
Bit 1 PLL2_FB_INT[9] PLL2 feedback integer divider 9 R/W 0
Bit 0 PLL2_FB_INT[8] PLL2 feedback integer divider 8 R/W 0
Byte 11h Name Control Function Type 0 1 PWD
Bit 7 PLL2_FB_INT_DIV[7] PLL2 feedback integer divider 7 R/W 0
Bit 6 PLL2_FB_INT_DIV[6] PLL2 feedback integer divider 6 R/W 0
Bit 5 PLL2_FB_INT_DIV[5] PLL2 feedback integer divider 5 R/W 1
Bit 4 PLL2_FB_INT_DIV[4] PLL2 feedback integer divider 4 R/W 1
Bit 3 PLL2_FB_INT_DIV[3] PLL2 feedback integer divider 3 R/W 1
Bit 2 PLL2_FB_INT_DIV[2] PLL2 feedback integer divider 2 R/W 1
Bit 1 PLL2_FB_INT_DIV[1] PLL2 feedback integer divider 1 R/W 0
Bit 0 PLL2_FB_INT_DIV[0] PLL2 feedback integer divider 0 R/W 0
20©2017 Integrated Device Technology, Inc. October 24, 2017
5L2503 Datasheet
Byte 18: PLL2 Fractional Feedback Divider
Byte 19: PLL2 Fractional Feedback Divider
Byte 20: PLL2 Spread Spectrum Control
Byte 12h Name Control Function Type 0 1 PWD
Bit 7 PLL2_FB_FRC_DIV[7] PLL2 feedback fractional divider 7 R/W 0
Bit 6 PLL2_FB_FRC_DIV[6] PLL2 feedback fractional divider 6 R/W 0
Bit 5 PLL2_FB_FRC_DIV[5] PLL2 feedback fractional divider 5 R/W 0
Bit 4 PLL2_FB_FRC_DIV[4] PLL2 feedback fractional divider 4 R/W 0
Bit 3 PLL2_FB_FRC_DIV[3] PLL2 feedback fractional divider 3 R/W 0
Bit 2 PLL2_FB_FRC_DIV[2] PLL2 feedback fractional divider 2 R/W 0
Bit 1 PLL2_FB_FRC_DIV[1] PLL2 feedback fractional divider 1 R/W 0
Bit 0 PLL2_FB_FRC_DIV[0] PLL2 feedback fractional divider 0 R/W 0
Byte 13h Name Control Function Type 0 1 PWD
Bit 7 PLL2_FB_FRC_DIV[15] PLL2 feedback fractional divider 15 R/W 0
Bit 6 PLL2_FB_FRC_DIV[14] PLL2 feedback fractional divider 14 R/W 0
Bit 5 PLL2_FB_FRC_DIV[13] PLL2 feedback fractional divider 13 R/W 0
Bit 4 PLL2_FB_FRC_DIV[12] PLL2 feedback fractional divider 12 R/W 0
Bit 3 PLL2_FB_FRC_DIV[11] PLL2 feedback fractional divider 11 R/W 0
Bit 2 PLL2_FB_FRC_DIV[10] PLL2 feedback fractional divider 10 R/W 0
Bit 1 PLL2_FB_FRC_DIV[9] PLL2 feedback fractional divider 9 R/W 0
Bit 0 PLL2_FB_FRC_DIV[8] PLL2 feedback fractional divider 8 R/W 0
Byte 14h Name Control Function Type 0 1 PWD
Bit 7 PLL2_STEP[7] PLL2 spread step size control bit 7 R/W 0
Bit 6 PLL2_STEP[6] PLL2 spread step size control bit 6 R/W 0
Bit 5 PLL2_STEP[5] PLL2 spread step size control bit 5 R/W 0
Bit 4 PLL2_STEP[4] PLL2 spread step size control bit 4 R/W 0
Bit 3 PLL2_STEP[3] PLL2 spread step size control bit 3 R/W 0
Bit 2 PLL2_STEP[2] PLL2 spread step size control bit 2 R/W 0
Bit 1 PLL2_STEP[1] PLL2 spread step size control bit 1 R/W 0
Bit 0 PLL2_STEP[0] PLL2 spread step size control bit 0 R/W 0
21©2017 Integrated Device Technology, Inc. October 24, 2017
5L2503 Datasheet
Byte 21: PLL2 Spread Spectrum Control
Byte 22: PLL2 Spread Spectrum Control
Byte 23: PLL2 Period Control
Byte 15h Name Control Function Type 0 1 PWD
Bit 7 PLL2_STEP[15] PLL2 spread step size control bit 15 R/W 0
Bit 6 PLL2_STEP[14] PLL2 spread step size control bit 14 R/W 0
Bit 5 PLL2_STEP[13] PLL2 spread step size control bit 13 R/W 0
Bit 4 PLL2_STEP[12] PLL2 spread step size control bit 12 R/W 0
Bit 3 PLL2_STEP[11] PLL2 spread step size control bit 11 R/W 0
Bit 2 PLL2_STEP[10] PLL2 spread step size control bit 10 R/W 0
Bit 1 PLL2_STEP[9] PLL2 spread step size control bit 9 R/W 0
Bit 0 PLL2_STEP[8] PLL2 spread step size control bit 8 R/W 0
Byte 16h Name Control Function Type 0 1 PWD
Bit 7 PLL2_STEP_DELTA[7] PLL2 spread step size control delta bit 7 R/W 0
Bit 6 PLL2_STEP_DELTA[6] PLL2 spread step size control delta bit 6 R/W 0
Bit 5 PLL2_STEP_DELTA[5] PLL2 spread step size control delta bit 5 R/W 0
Bit 4 PLL2_STEP_DELTA[4] PLL2 spread step size control delta bit 4 R/W 0
Bit 3 PLL2_STEP_DELTA[3] PLL2 spread step size control delta bit 3 R/W 0
Bit 2 PLL2_STEP_DELTA[2] PLL2 spread step size control delta bit 2 R/W 0
Bit 1 PLL2_STEP_DELTA[1] PLL2 spread step size control delta bit 1 R/W 0
Bit 0 PLL2_STEP_DELTA[0] PLL2 spared step size control delta bit 0 R/W 0
Byte 17h Name Control Function Type 0 1 PWD
Bit 7 PLL2_PERIOD[7] PLL2 period control bit 7 R/W 0
Bit 6 PLL2_PERIOD[6] PLL2 period control bit 6 R/W 0
Bit 5 PLL2_PERIOD[5] PLL2 period control bit 5 R/W 0
Bit 4 PLL2_PERIOD[4] PLL2 period control bit 4 R/W 0
Bit 3 PLL2_PERIOD[3] PLL2 period control bit 3 R/W 0
Bit 2 PLL2_PERIOD[2] PLL2 period control bit 2 R/W 0
Bit 1 PLL2_PERIOD[1] PLL2 period control bit 1 R/W 0
Bit 0 PLL2_PERIOD[0] PLL2 period control bit 0 R/W 0

5L2503-000NVGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products Microclock Programmable Clock Generator
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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