7©2017 Integrated Device Technology, Inc. October 24, 2017
5L2503 Datasheet
Table 11. Output Dividers 2, 3, and 5
Table 12. Output Divider 4
Output Clock Test Conditions
Output Divider Bits <1:0>
Output Divider Bits <3:2>
00 01 10 11
00 1245
01 3 6 12 15
10 5 102025
11 10 20 40 50
Output Divider Bits <1:0>
Output Divider Bits <3:2>
00 01 10 11
00 1248
01 4 8 16 32
10 5 102040
11 6 122448
2 inches
2pF
33ohm
LVCMOS
LVCMOS Output Test Conditions
50ohm
8©2017 Integrated Device Technology, Inc. October 24, 2017
5L2503 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 5L2503 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions
may affect device reliability.
Table 13: Absolute Maximum Ratings
Recommended Operating Conditions
Item Rating
Supply Voltage, V
DD1_8,
V
DDOUTx
1.89V
Inputs
Other Inputs -0.5V to V
DD1_8
/V
DDOUTx
Outputs, V
DDOUTx
(LVCMOS) -0.5V to V
DDOUTx
+ 0.5V
Outputs, IO (SDA) 10mA
Package Thermal Impedance, Θ
JA
42°C/W (0 mps)
Package Thermal Impedance, Θ
JC
41.8°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
ESD Human Body Model 2000V
Junction Temperature 125°C
Table 14: Recommended Operating Conditions
Symbol Parameter Minimum Typical Maximum Units
V
DDOUTx
Power supply voltage for supporting 1.8V output and all other
outputs.
1.71 1.8 1.89 V
V
DD1_8
Power supply voltage for core logic functions. 1.71 1.8 1.89 V
T
A
Operating temperature, ambient. -40 85 °C
C
LOAD_OUT
Maximum load capacitance (1.8V LVCMOS only). 5 pF
t
PU
Power up time for all V
DD
s to reach minimum specified voltage
(power ramps must be monotonic).
0.05 3 ms
9©2017 Integrated Device Technology, Inc. October 24, 2017
5L2503 Datasheet
Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down
Resistance
(T
A
= +25 °C)
Recommended Crystal Characteristics
DC Electrical Characteristics
1
Single CMOS driver active.
2
OUT1–3 current measured with 0.5 inches transmission line and no load.
Table 15: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance
Symbol Parameter Minimum Typical Maximum Units
C
IN
Input Capacitance (OE, SDA, SCL) 3 7 pF
Pull-down Resistor OE 150 k
R
OUT
LVCMOS Output Driver Impedance (V
DDOUTx
= 1.8V) 17
Table 16: Crystal Characteristics
Parameter Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 8 48 MHz
Frequency Tolerance -20 20 ppm
Equivalent Series Resistance (ESR) 10 100
Shunt Capacitance 2 7 pF
Load Capacitance (C
L
)6810pF
Maximum Crystal Drive Level 100 μW
Table 17: DC Electrical Characteristics
Symbol Parameter Conditions Minimum Typical Maximum Units
I
DD
Operation Supply
Current
V
DD
= V
DDO
= V
DD1_8
= 1.8V; OUT1 = 12MHz,
OUT3 = 26MHz, OUT2 off, no load.
2.0 mA
V
DD
= V
DDO
= V
DD1_8
= 1.8V; OUT1 = 12MHz,
OUT3 = 26MHz, OUT2 off, with load.
3.5 mA
V
DD
= V
DDO
= V
DD1_8
= 1.8V; OUT1 = 26MHz,
OUT3 = 26MHz, OUT2 = 32kHz, no load.
1.8 mA
V
DD
= V
DDO
= V
DD1_8
= 1.8V; OUT1 = 26MHz,
OUT3 = 26MHz, OUT2 = 32kHz, with load.
3.8 mA
I
DDPD
Power Down
Current
PD asserted with V
DD1_8
and V
DDO
ON, I
2
C
programming, 32k running.
390 μA
I
DDSUSPEND
Power Suspend
Current
V
DDOUT2
OFF and only V
DDOUT1
and V
DD1_8
ON, I
2
C programming, 32k running.
1.6 2.0 μA

5L2503-000NVGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products Microclock Programmable Clock Generator
Lifecycle:
New from this manufacturer.
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