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5L2503-000NVGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
4©2017 Integrated Device Technology, Inc. October 24, 2017
5L2503 Datasheet
Device Features and Functions
DFC – Dynamic Frequency Control
▪ OTP programmable–4 different feedback fractional dividers (4 VCO frequencies) that apply to PLL2.
▪ ORT (overshoot reduction) function will be applied automatically during the VCO frequency change.
▪ Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection.
Figure 2. DFC Function Block Diagram
Table 7. DFC Function Priority
* See OE Pin Function table.
DFC Function Programming
▪ Register B63b3:2 select DFC00–DFC11 configuration.
▪ Byte16–19 are the register for PLL2 VCO setting. Based on B63b3:2 configuration selection, the data write to B16–19 will be stored in
selected configuration OTP memory.
▪ Refer to DFC Function Priority table; select proper control pin(s) to activate DFC function.
▪ Note the DFC function can also be controlled by I
2
C access.
DFC Mode OE Pin
DFC_EN bit
(W32[4])
OE1_fun_sel I
2
C Pins SCL_DFC1 SDA_DFC0 DFC[1:0] Notes
Off OE In * 0 00 or 01 or 10 *
Active (SCL =
1 at POR)
SCL input SDA I/O
Not
applicable
DFC disable
On DFC0 In 1 11 Active SCL input SDA I/O DFC0 = OE
One pin DFC
via OE1
On OE In * 1 00 or 01 or 10 *
Inactive (SCL=
0 at POR)
DFC1 DFC0
DFC1 =
SCL_DFC1
I
2
C pin as DFC
control pins
On OE In * 1 00 or 01 or 10 *
Active (SCL =
1 at POR)
SCL input SDA I/O W30[1:0]
I
2
C control
DFC mode
PLL2
Mdivider
Ndivider
Ndivider
Ndivider
Ndivider
Selector
00
01
10
11
DFC1: 0
OTP/I2C
OUTDIV
5©2017 Integrated Device Technology, Inc. October 24, 2017
5L2503 Datasheet
PPS – Proactive Power Saving Function
PPS Proactive Power Saving is an IDT patented unique design for the clock generator that proactively detects end device power-down
state and then switches output clocks between normal operation clock frequency and low power mode 32kHz clock that only consumes
< 5μA current. The system could save power when the device goes into power-down or sleep mode. The PPS function diagram is shown
below.
Figure 3. PPS Function Block Diagram
Figure 4. PPS Assertion/Deassertion Timing Chart
PPS Function Programming
▪ Refer to OE_pin_function_table to have proper PPS function selected for OE pin(s); note that register default is set to Output Enable
(OE) function for OE pins.
I
2
C
&
Logic
Xtal
Oscillator
PLL
PPS
Control
Logic
Low
Power
DCO
Logic
Power
Down
Control
Xtal
Oscillator
XIN
XOUT
MHz / kHz
Switching
PPS assertion
PPS deassertion
1st cycle
2nd cycle
3rd cycle
1st cycle
2nd cycle
32kHz clocks
32kHz clocksMHz clock
MHz clock
6©2017 Integrated Device Technology, Inc. October 24, 2017
5L2503 Datasheet
Input Pin Function
The input pins in 5L2503 have multiple functions. The OE1 pin can be configured as output enable control (OE) or chip power-down
control (PD#) or Proactive Power Saving function (PPS). Furthermore, the OE1 pin can be configured as a single or two-pin Dynamic
Frequency Control (DFC).
SCL/SDA are also multiple function pins. The two pins can be configured as output enable control (OE), or I
2
C interface or Dynamic
Frequency Control (DFC) functions by programming and hardware pin latch.
Table 8. OE1 Pin Function
Table 9. SDA/SCL Function
Spread Spectrum
The 5L2503 supports spread spectrum clocks from PLL1. PLL1 has built-in analog spread spectrum; PLL2 and PLL3 use seed clock from
PLL1.
ORT – VCO Overshoot Reduction Technology
The 5L2503 supports innovate the VCO overshoot reduction technology to prevent the output clock frequency spike when the device is
change frequency on the fly or doing DFC (Dynamic Frequency Control) function. The VCO frequency change are under control instead
of freerun to targeted frequency.
PLL Features and Descriptions
Table 10. Output Divider 1
Function
Byte30
bit6 bit5
OUT1 output enable/disable 0 0
Global Power Down (PD#) 0 1
OUT1 Proactive Power Saving Input (OUT1 PPS) 1 0
DFC0 1 1
SEL_DFC (latched) Enable OE2/3 B36<2> DFC_EN B32<4> OE1 Funsel B30<6:5> Function of SCL/SDA
0 0 0 00, 01, 10 N/A
0 0 1 00, 01, 10 SCL = DFC1, SDA = DFC0
0 1 X 00, 01, 10 SCL = OE3, SDA = OE2
1 X X 00, 01, 10 SCL, SDA
Output Divider Bits <1:0>
Output Divider Bits <3:2>
00 01 10 11
00 1248
01 4 8 16 32
10 5 102040
11 6 122448
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

5L2503-000NVGI

Mfr. #:
Buy 5L2503-000NVGI
Manufacturer:
IDT
Description:
Clock Generators & Support Products Microclock Programmable Clock Generator
Lifecycle:
New from this manufacturer.
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