1. General description
The SAA7102; SAA7103 is used to encode PC graphics data at maximum 800 × 600
resolution to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and
interlacer ensures properly sized and flicker-free TV display as CVBS or S-video output.
Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals
together with a TTL composite sync to feed SCART connectors.
When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the
RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor
at maximum 800 × 600 resolution/60 Hz (PIXCLK < 45 MHz).
The device includes a sync/clock generator and on-chip DACs.
2. Features
Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for
TV output from a PC
27 MHz crystal-stable subcarrier generation
Maximum graphics pixel clock 45 MHz at double edged clocking, synthesized on-chip
or from external source
Up to 800 × 600 graphics data at 60 Hz or 50 Hz with programmable underscan range.
Three Digital-to-Analog Converters (DACs) at 27 MHz sample rate for CVBS (BLUE,
C
B
), VBS (GREEN, CVBS) and C (RED, C
R
) (signals in parenthesis are optional); all at
10-bit resolution
Non-Interlaced (NI) C
B
-Y-C
R
or RGB input at maximum 4 : 4 : 4 sampling
Downscaling from 1 : 1 to 1 : 2 and up to 20 % upscaling
Optional interlaced C
B
-Y-C
R
input of Digital Versatile Disc (DVD) signals
Optional non-interlaced RGB output to drive second VGA monitor (bypass mode with
maximum 45 MHz)
3 × 256 bytes RGB Look-Up Table (LUT)
Support for hardware cursor
Programmable border color of underscan area
On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal)
Fast I
2
C-bus control port (400 kHz)
Encoder can be master or slave
Programmable horizontal and vertical input synchronization phase
Programmable horizontal sync output phase
Internal Color Bar Generator (CBG)
Optional support of various Vertical Blanking Interval (VBI) data insertion
SAA7102; SAA7103
Digital video encoder
Rev. 04 — 18 January 2006 Product data sheet
SAA7102_SAA7103_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 18 January 2006 2 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Macrovision Pay-per-View copy protection system rev. 7.01 and rev. 6.1 as option; this
applies to the SAA7102 only
Power-save modes
Joint Test Action Group (JTAG) Boundary Scan Test (BST)
Monolithic CMOS 3.3 V device, 5 V tolerant I/Os
QFP44 and LBGA156 packages
Same footprint as SAA7108E; SAA7109E
3. Quick reference data
4. Ordering information
Table 1: Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
V
DDA
analog supply voltage 3.15 3.3 3.45 V
V
DDD
digital supply voltage 3.0 3.3 3.6 V
I
DDA
analog supply current 1 110 140 mA
I
DDD
digital supply current 1 70 90 mA
V
i
input signal voltage levels TTL compatible
V
o(p-p)
analog CVBS output signal
voltage for a 100/100 color bar
at 75/2 load
(peak-to-peak value)
- 1.23 - V
R
L
load resistance - 37.5 -
ILE
lf(DAC)
low frequency integral linearity
error of DACs
--±3 LSB
DLE
lf(DAC)
low frequency differential
linearity error of DACs
--±1 LSB
T
amb
ambient temperature 0 - 70 °C
Table 2: Ordering information
Type number Package
Name Description Version
SAA7102E LBGA156 plastic low profile ball grid array package; 156 balls;
body 15 × 15 × 1.05 mm
SOT700-1
SAA7103E
SAA7102H QFP44 plastic quad flat package; 44 leads (lead length
1.3 mm); body 10 × 10 × 1.75 mm
SOT307-2
SAA7103H
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
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SAA7102_SAA7103_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 18 January 2006 3 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
5. Block diagram
Fig 1. Block diagram (SAA7102H and SAA7103H)
VERTICAL
SCALER AND
ANTI-FLICKER
FILTER
FIFO
HORIZONTAL
SCALER
DECIMATOR
4 : 4 : 4 to 4 : 2 : 2
(OR BYPASS)
TRIPLE
DAC
BLUE_CB_CVBS
GREEN_VBS_CVBS
RED_CR_C
30
28
27
HSM_CSYNC
26
VSM
25
VIDEO
ENCODER
BORDER
GENERATOR
CURSOR
INSERTION
RGB TO Y-C
B
-C
R
MATRIX
(OR BYPASS)
RGB LUT
(OR BYPASS)
I
2
C-BUS
CONTROL
OSCILLATOR/
DTO
TIMING
GENERATOR
13343523
FSVGC
VSVGC
XTALO
27 MHz
TTX_SRES
XTALI
HSVGC
CBO
TTXRQ_XCLKO2
14 21
12
SDA
SCL
11 522 24
CGC
LOW-PASS
INPUT
FORMATTER
V
DDD1
10
4 to 1,
44 to 41,
16 to 19
V
SSD1
9
15
PD11 to
PD0
PIXCLKI
20
PIXCLKO
V
DDD2
40
V
SSD2
39
V
DDA2
36
V
DDA1
29
V
SSA1
33
DUMP
32
RSET
31
TDI
38
TRST
37
TCK
8
TMS
6
TDO
7
mhb963
SAA7102H
SAA7103H
RESET

SAA7103H/V4,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC DIGITAL VIDEO ENCODER 44QFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union