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SAA7103H/V4,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84
SAA7102_SAA7103_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 18 January 2006 55 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
[1] Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed.
5 TTXEN R/W teletext insertion
0* disabled
1 enabled
4 to 0 SCCLN[4:0] R/W - selects the actual line, where closed caption or extended
data are encoded; line = (SCCLN + 4) for M-systems;
line = (SCCLN + 1) for other systems
Table 62: Active Display Window Horizontal (ADWH) start and end registers,
subaddresses 70h to 72h, bit description
Subaddress Bit Symbol Access Value Description
70h 7 to 0 ADWHS[7:0] R/W - active display window horizontal start;
defines the start of the active TV display
portion after the border color
[1]
71h 7 to 0 ADWHE[7:0] R/W - active display window horizontal end;
defines the end of the active TV display
portion before the border color
[1]
72h 7 - R/W 0 must be programmed with logic 0 to ensure
compatibility to future enhancements
6 to 4 ADWHE[10:8] R/W - active display window horizontal end;
defines the end of the active TV display
portion before the border color
[1]
3 - R/W 0 must be programmed with logic 0 to ensure
compatibility to future enhancements
2 to 0 ADWHS[10:8] R/W - active display window horizontal start;
defines the start of the active TV display
portion after the border color
[1]
Table 63: TTX request horizontal start register, subaddress 73h, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 to 0 TTXHS[7:0] R/W start of signal TTXRQ on pin TTXRQ_XCLKO2
(CLK2EN = 0); see
Figure 15
42h* if strapped to PAL
54h* if strapped to NTSC
Table 64: TTX request horizontal delay register, subaddress 74h, bit description
Legend: * = default value after reset and minimum value.
Bit Symbol Access Value Description
7 to 4 - R/W 0h must be programmed with logic 0 to ensure compatibility
to future enhancements
3 to 0 TTXHD[3:0] R/W 2h* indicates the delay in clock cycles between rising edge of
TTXRQ output signal on pin TTXRQ_XCLKO2
(CLK2EN = 0) and valid data at pin TTX_SRES
Table 61: Closed caption, teletext enable register, subaddress 6Fh, bit description
…continued
Bit Symbol Access Value Description
SAA7102_SAA7103_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 18 January 2006 56 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 65: CSYNC advance register, subaddress 75h, bit description
Bit Symbol Access Value Description
7 to 3 CSYNCA[4:0] R/W - advanced composite sync against RGB output from
0 XTAL clocks to 31 XTAL clocks
2 to 0 - R/W 000 must be programmed with logic 0 to ensure compatibility
to future enhancements
Table 66: TTX odd request vertical start register, subaddress 76h, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 to 0 TTXOVS[7:0] R/W with TTXOVS8 (see
Table 72) first line of occurrence of
signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in
odd field, line = (TTXOVS + 4) for M-systems and
line = (TTXOVS + 1) for other systems
05h* if strapped to PAL
06h* if strapped to NTSC
Table 67: TTX odd request vertical end register, subaddress 77h, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 to 0 TTXOVE[7:0] R/W with TTXOVE8 (see
Table 72) last line of occurrence of
signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in
odd field, line = (TTXOVE + 3) for M-systems and
line = TTXOVE for other systems
16h* if strapped to PAL
10h* if strapped to NTSC
Table 68: TTX even request vertical start register, subaddress 78h, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 to 0 TTXEVS[7:0] R/W with TTXEVS8 (see
Table 72) first line of occurrence of
signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in
even field, line = (TTXEVS + 4) for M-systems and
line = (TTXEVS + 1) for other systems
04h* if strapped to PAL
05h* if strapped to NTSC
Table 69: TTX even request vertical end register, subaddress 79h, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 to 0 TTXEVE[7:0] R/W with TTXEVE8 (see
Table 72) last line of occurrence of
signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in
even field, line = (TTXEVE + 3) for M-systems and
line = TTXEVE for other systems
16h* if strapped to PAL
10h* if strapped to NTSC
SAA7102_SAA7103_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 18 January 2006 57 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
[1] This bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE.
Table 70: First active line register, subaddress 7Ah, bit description
Bit Symbol Access Value Description
7 to 0 FAL[7:0] R/W with FAL8 (see
Table 72) first active line = (FAL + 4) for
M-systems and (FAL + 1) for other systems, measured in
lines
00h coincides with the first field synchronization pulse
Table 71: Last active line register, subaddress 7Bh, bit description
Bit Symbol Access Value Description
7 to 0 LAL[7:0] R/W with LAL8 (see
Table 72) last active line = (LAL + 3) for
M-systems and LAL for other system, measured in lines
00h coincides with the first field synchronization pulse
Table 72: TTX mode, MSB vertical register, subaddress 7Ch, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 TTX60 R/W 0* enables NABTS (FISE = 1) or European TTX (FISE = 0)
1 enables world standard teletext 60 Hz (FISE = 1)
6 LAL8 R/W see
Table 71
5 - R/W 0 must be programmed with logic 0 to ensure compatibility to
future enhancements
4 FAL8 R/W see
Table 70
3 TTXEVE8 R/W see
Table 69
2 TTXOVE8 R/W see
Table 67
1 TTXEVS8 R/W see
Table 68
0 TTXOVS8 R/W see
Table 66
Table 73: Disable TTX line registers, subaddresses 7Eh and 7Fh, bit description
[1]
Subaddress Bit Symbol Access Value Description
7Eh 7 to 0 LINE[12:5] R/W - individual lines in both fields (PAL counting)
can be disabled for insertion of teletext by the
respective bits, disabled line = LINExx (50 Hz
field rate)
7Fh 7 to 0 LINE[20:13] R/W -
Table 74: Pixel clock 0, 1 and 2 registers, subaddresses 81h to 83h, bit description
Subaddress Bit Symbol Access Value Description
81h 7 to 0 PCL[07:00] R/W defines the frequency of the synthesized
pixel clock PIXCLKO;
;
f
XTAL
= 27 MHz nominal
82h 7 to 0 PCL[15:08]
83h 7 to 0 PCL[23:16]
20 F63Bh 640 × 480 to NTSC M
1B 5A73h 640 × 480 to PAL B/G (as by strapping
pins)
f
PIXCLK
PCL
2
24
-----------
f
XTAL
×
⎝⎠
⎛⎞
8
×=
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84

SAA7103H/V4,518

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Buy SAA7103H/V4,518
Manufacturer:
NXP Semiconductors
Description:
IC DIGITAL VIDEO ENCODER 44QFP
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New from this manufacturer.
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