OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

SAA7103H/V4,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84
SAA7102_SAA7103_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 18 January 2006 52 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 54: CCR and blanking level VBI register, subaddress 5Fh, bit description
Bit Symbol Access Value Description
7 and 6 CCRS[1:0] R/W select cross-color reduction filter in luminance; for overall
transfer characteristic of luminance see Figure 8
00 no cross-color reduction
01 cross-color reduction #1 active
10 cross-color reduction #2 active
11 cross-color reduction #3 active
5 to 0 BLNVB[5:0] R/W - variable blanking level during vertical blanking interval is
typically identical to value of BLNNL
Table 55: Standard control register, subaddress 61h, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 DOWND R/W digital core
0* in normal operational mode
1 in Sleep mode and is reactivated with an I
2
C-bus address
6 DOWNA R/W DACs
0* in normal operational mode
1 in Power-down mode
5 - R/W 0 must be programmed with logic 0 to ensure compatibility
to future enhancements
4 YGS R/W luminance gain for white − black
0 100 IRE
1 92.5 IRE including 7.5 IRE set-up of black
3 - R/W 0 must be programmed with logic 0 to ensure compatibility
to future enhancements
2 SCBW R/W bandwidth for chrominance encoding (for overall transfer
characteristic of chrominance in baseband representation
see
Figure 6 and Figure 7)
0 enlarged
1* standard
1 PAL R/W encoding
0 NTSC (non-alternating V component)
1 PAL (alternating V component)
0 FISE R/W total pixel clocks per line
0 864
1 858
SAA7102_SAA7103_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 18 January 2006 53 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
[1]
Examples:
a) NTSC M: f
fsc
= 227.5, f
llc
= 1716 → FSC = 569408543 (21F0 7C1Fh).
b) PAL B/G: f
fsc
= 283.7516, f
llc
= 1728 → FSC = 705268427 (2A09 8ACBh).
[1] LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the
respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format.
Table 56: Burst amplitude register, subaddress 62h, bit description
Legend: * = default value after reset, ^ = recommended value.
Bit Symbol Access Value Description
7 - R/W 0 must be programmed with logic 0 to ensure compatibility to
future enhancements
6 to 0 BSTA[6:0] R/W amplitude of color burst; input representation in accordance
with ‘ITU-R BT.601’
3Fh
(63)^
white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding;
BSTA = 0 to 2.02 × nominal
2Dh
(45)^
white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding;
BSTA = 0 to 2.82 × nominal
43h
(67)^
white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding;
BSTA = 0 to 1.90 × nominal
2Fh
(47)*^
white-to-black = 100 IRE; burst = 43 IRE; PAL encoding;
BSTA = 0 to 3.02 × nominal
Table 57: Subcarrier 0, 1, 2 and 3 registers, subaddresses 63h to 66h, bit description
Subaddress Bit Symbol Access Value Description
66h 7 to 0 FSC[31:24] R/W - f
fsc
= subcarrier frequency (in multiples of line
frequency); f
llc
= clock frequency (in multiples
of line frequency); FSC[31:24] = most
significant byte; FSC[07:00] = least significant
byte
[1]
65h 7 to 0 FSC[23:16] R/W -
64h 7 to 0 FSC[15:08] R/W -
63h 7 to 0 FSC[07:00] R/W -
Table 58: Line 21 odd 0, 1 and even 0, 1 registers, subaddresses 67h to 6Ah, bit
description
[1]
Subaddress Bit Symbol Access Value Description
67h 7 to 0 L21O[07:00] R/W - first byte of captioning data, odd field
68h 7 to 0 L21O[17:10] R/W - second byte of captioning data, odd field
69h 7 to 0 L21E[07:00] R/W - first byte of extended data, even field
6Ah 7 to 0 L21E[17:10] R/W - second byte of extended data, even field
Table 59: Trigger control registers, subaddresses 6Ch and 6Dh, bit description
Legend: * = default value after reset.
Subaddress Bit Symbol Access Value Description
6Ch 7 to 0 HTRIG[7:0] R/W 00h* sets the horizontal trigger phase related to
chip-internal horizontal input
[1]
6Dh 7 to 5 HTRIG[10:8] R/W 0h*
4 to 0 VTRIG[4:0] R/W 00h* sets the vertical trigger phase related to
chip-internal vertical input
[2]
F
SC round
f
fsc
f
llc
----------
2
32
×
⎝⎠
⎛⎞
=
SAA7102_SAA7103_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 18 January 2006 54 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
[1] Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of
all internally generated timing signals.
[2] Increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1Fh).
Table 60: Multi control register, subaddress 6Eh, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 - R/W 0 must be programmed with logic 0 to ensure compatibility
to future enhancements
6 BLCKON R/W 0* encoder in normal operation mode
1 output signal is forced to blanking level
5 and 4 PHRES[1:0] R/W selects the phase reset mode of the color subcarrier
generator
00 no subcarrier reset
01 subcarrier reset every two lines
10 subcarrier reset every eight fields
11 subcarrier reset every four fields
3 and 2 LDEL[1:0] R/W selects the delay on luminance path with reference to
chrominance path
00* no luminance delay
01 1 LLC luminance delay
10 2 LLC luminance delay
11 3 LLC luminance delay
1 and 0 FLC[1:0] R/W field length control
00* interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at
60 Hz
01 non-interlaced 312 lines/field at 50 Hz, 262 lines/field at
60 Hz
10 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at
60 Hz
11 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at
60 Hz
Table 61: Closed caption, teletext enable register, subaddress 6Fh, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 and 6 CCEN[1:0] R/W enables individual line 21 encoding
00* line 21 encoding off
01 enables encoding in field 1 (odd)
10 enables encoding in field 2 (even)
11 enables encoding in both fields
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84

SAA7103H/V4,518

Mfr. #:
Buy SAA7103H/V4,518
Manufacturer:
NXP Semiconductors
Description:
IC DIGITAL VIDEO ENCODER 44QFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet