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SAA7103H/V4,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84
SAA7102_SAA7103_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 18 January 2006 49 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
Table 46: Gain luminance for RGB register, subaddress 38h, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 to 5 - R/W 0 must be programmed with logic 0 to ensure compatibility to
future enhancements
4 to 0 GY[4:0] R/W - Gain luminance of RGB (C
R
, Yand C
B
) output, ranging from
(1 −
16
⁄
32
)to(1+
15
⁄
32
). Suggested nominal value = 0,
depending on external application.
Table 47: Gain color difference for RGB register, subaddress 39h, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 to 5 - R/W 0 must be programmed with logic 0 to ensure compatibility to
future enhancements
4 to 0 GCD[4:0] R/W - Gain color difference of RGB (C
R
, Yand C
B
) output, ranging
from (1 −
16
⁄
32
)to(1+
15
⁄
32
). Suggested nominal value = 0,
depending on external application.
Table 48: Input port control 1 register, subaddress 3Ah, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 CBENB R/W 0 data from input ports is encoded
1 color bar with fixed colors is encoded
6 and 5 - R/W 0 must be programmed with logic 0 to ensure compatibility to
future enhancements
4 SYMP R/W horizontal and vertical trigger
0* taken from FSVGC or both VSVGC and HSVGC
1 decoded out of ‘ITU-R BT.656’ compatible data at PD port
3 DEMOFF R/W Y-C
B
-C
R
to RGB dematrix
0* active
1 bypassed
2 CSYNC R/W pin HSM_CSYNC provides
0 horizontal sync for non-interlaced VGA components output
(at PIXCLK)
1 composite sync for interlaced components output (at XTAL
clock)
1 Y2C R/W input luminance data
0 twos complement from PD input port
1* straight binary from PD input port
0 UV2C R/W input color difference data
0 twos complement from PD input port
1* straight binary from PD input port
SAA7102_SAA7103_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 18 January 2006 50 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
[1] In line 16; LSB first; all other bytes are not relevant for VPS.
Table 49: VPS enable, input control 2, subaddress 54h, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 VPSEN R/W video programming system data insertion
0* is disabled
1 in line 16 is enabled
6 to 2 - R/W 0 must be programmed with logic 0 to ensure compatibility to
future enhancements
1 EDGE2 R/W internal PPD2 data is sampled with
0 rising clock edges
1* falling clock edges; see
Table 28 to Table 34
0 EDGE1 R/W internal PPD1 data is sampled with
0* rising clock edges
1 falling clock edges; see
Table 28 to Table 34
Table 50: VPS byte 5, 11, 12, 13 and 14 registers, subaddresses 55h to 59h, bit
description
[1]
Subaddress Bit Symbol Access Value Description
55h 7 to 0 VPS5[7:0] R/W - fifth byte of video programming system data
56h 7 to 0 VPS11[7:0] R/W - eleventh byte of video programming system
data
57h 7 to 0 VPS12[7:0] R/W - twelfth byte of video programming system
data
58h 7 to 0 VPS13[7:0] R/W - thirteenth byte of video programming system
data
59h 7 to 0 VPS14[7:0] R/W - fourteenth byte of video programming system
data
Table 51: Chrominance phase register, subaddress 5Ah, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 to 0 CHPS[7:0] R/W 00h* phase of encoded color subcarrier (including burst) relative
to horizontal sync; can be adjusted in steps of
360/256 degrees
6Bh PAL B/G and data from input ports in Master mode
16h PAL B/G and data from look-up table
25h NTSC M and data from input ports in Master mode
46h NTSC M and data from look-up table
SAA7102_SAA7103_4 © Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet Rev. 04 — 18 January 2006 51 of 84
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
[1] Variable gain for C
B
signal; input representation in accordance with ‘ITU-R BT.601’.
[2] Variable black level; input representation in accordance with ‘ITU-R BT.601’.
[3] Output black level/IRE = BLCKL × 2/6.29 + 28.9.
[4] Output black level/IRE = BLCKL × 2/6.18 + 26.5.
[1] Variable gain for C
R
signal; input representation in accordance with ‘ITU-R BT.601’.
[2] Variable blanking level.
[3] Output black level/IRE = BLNNL × 2/6.29 + 25.4.
[4] Output black level/IRE = BLNNL × 2/6.18 + 25.9; default after reset: 35h.
Table 52: Gain U and gain U MSB, black level registers, subaddresses 5Bh and 5Dh, bit description
Subaddress Bit Symbol Conditions Remarks
5Bh 7 to 0 GAINU[8:0]
[1]
white-to-black = 92.5 IRE GAINU = −2.17 × nominal to +2.16 × nominal
5Dh 7 GAINU = 0 output subcarrier of U contribution = 0
GAINU = 118 (76h) output subcarrier of U contribution = nominal
white-to-black = 100 IRE GAINU = −2.05 × nominal to +2.04 × nominal
GAINU = 0 output subcarrier of U contribution = 0
GAINU = 125 (7Dh) output subcarrier of U contribution = nominal
6 - must be programmed with logic 0 to ensure compatibility to future
enhancements
5 to 0 BLCKL[5:0]
[2]
white-to-sync = 140 IRE
[3]
recommended value: BLCKL = 58 (3Ah)
BLCKL = 0
[3]
output black level = 29 IRE
BLCKL = 63 (3Fh)
[3]
output black level = 49 IRE
white-to-sync = 143 IRE
[4]
recommended value: BLCKL = 51 (33h)
BLCKL = 0
[4]
output black level = 27 IRE
BLCKL = 63 (3Fh)
[4]
output black level = 47 IRE
Table 53: Gain V and gain V MSB, blanking level registers, subaddresses 5Ch and 5Eh, bit description
Subaddress Bit Symbol Conditions Remarks
5Ch 7 to 0 GAINV[8:0]
[1]
white-to-black = 92.5 IRE GAINV = −1.55 × nominal to +1.55 × nominal
5Eh 7 GAINV = 0 output subcarrier of V contribution = 0
GAINV = 165 (A5h) output subcarrier of V contribution = nominal
white-to-black = 100 IRE GAINV = −1.46 × nominal to +1.46 × nominal
GAINV = 0 output subcarrier of V contribution = 0
GAINV = 175 (AFh) output subcarrier of V contribution = nominal
6 - must be programmed with logic 0 to ensure compatibility to future
enhancements
5 to 0 BLNNL[5:0]
[2]
white-to-sync = 140 IRE
[3]
recommended value: BLNNL = 46 (2Eh)
BLNNL = 0
[3]
output blanking level = 25 IRE
BLNNL = 63 (3Fh)
[3]
output blanking level = 45 IRE
white-to-sync = 143 IRE
[4]
recommended value: BLNNL = 53 (35h)
BLNNL = 0
[4]
output blanking level = 26 IRE
BLNNL = 63 (3Fh)
[4]
output blanking level = 46 IRE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84

SAA7103H/V4,518

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Buy SAA7103H/V4,518
Manufacturer:
NXP Semiconductors
Description:
IC DIGITAL VIDEO ENCODER 44QFP
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