SAA7103H/V4,518 Datasheet SAA7103E/V4,518, SAA7103E/V4,557, SAA7103H/V4,518 | P46-P48

Product data sheet Rev. 04 — 18 January 2006 46 of 84

Philips Semiconductors

SAA7102; SAA7103

Digital video encoder

Table 38: RGB DAC adjust coarse registers, subaddresses 17h to 19h, bit description

Subaddress Bit Symbol Description

17h to 19h 7 to 5 - must be programmed with logic 0 to ensure compatibility to

future enhancements

17h 4 to 0 RDACC[4:0] output level coarse adjustment for RED DAC; default after

reset is 1Bh for output of C signal

0 0000b ≡ 0.585 V to 1 1111b ≡ 1.240 V at 37.5 Ω nominal for

full-scale conversion

18h 4 to 0 GDACC[4:0] output level coarse adjustment for GREEN DAC; default after

reset is 1Bh for output of VBS signal

0 0000b ≡ 0.585 V to 1 1111b ≡ 1.240 V at 37.5 Ω nominal for

full-scale conversion

19h 4 to 0 BDACC[4:0] output level coarse adjustment for BLUE DAC; default after

reset is 1Fh for output of CVBS signal

0 0000b ≡ 0.585 V to 1 1111b ≡ 1.240 V at 37.5 Ω nominal for

full-scale conversion

Table 39: MSM threshold, subaddress 1Ah, bit description

Bit Symbol Description

7 to 0 MSMT[7:0] monitor sense mode threshold for DAC output voltage, should be set to 70h

Table 40: Monitor sense mode register, subaddress 1Bh, bit description

Legend: * = default value after reset.

Bit Symbol Access Value Description

7 MSM R/W monitor sense mode

0* off; RCOMP, GCOMP and BCOMP bits are not valid

1on

6 to 3 - R/W 0 must be programmed with logic 0 to ensure compatibility to

future enhancements

2 RCOMP R check comparator at DAC on pin RED_CR_C

0 active, output is loaded

1 inactive, output is not loaded

1 GCOMP R check comparator at DAC on pin GREEN_VBS_CVBS

0 active, output is loaded

1 inactive, output is not loaded

0 BCOMP R check comparator at DAC on pin BLUE_CB_CVBS

0 active, output is loaded

1 inactive, output is not loaded

Product data sheet Rev. 04 — 18 January 2006 47 of 84

Philips Semiconductors

SAA7102; SAA7103

Digital video encoder

Table 41: Wide screen signal registers, subaddresses 26h and 27h, bit description

Legend: * = default value after reset.

Subaddress Bit Symbol Access Value Description

27h 7 WSSON R/W 0* wide screen signalling output is disabled

1 wide screen signalling output is enabled

6 - R/W 0 must be programmed with logic 0 to ensure

compatibility to future enhancements

5 to 3 WSS[13:11] R/W - wide screen signalling bits, reserved

2 to 0 WSS[10:8] R/W - wide screen signalling bits, subtitles

26h 7 to 4 WSS[7:4] R/W - wide screen signalling bits, enhanced

services

3 to 0 WSS[3:0] R/W - wide screen signalling bits, aspect ratio

Table 42: Real-time control and burst start register, subaddress 28h, bit description

Legend: * = default value after reset.

Bit Symbol Access Value Description

7 and 6 - R/W 0 must be programmed with logic 0 to ensure compatibility to

future enhancements

5 to 0 BS[5:0] R/W starting point of burst in clock cycles

21h* PAL: BS = 33; strapping pin FSVGC tied to HIGH

19h* NTSC: BS = 25; strapping pin FSVGC tied to LOW

Table 43: Sync reset enable and burst end register, subaddress 29h, bit description

Legend: * = default value after reset.

Bit Symbol Access Value Description

7 SRES R/W 0* pin TTX_SRES accepts a teletext bit stream (TTX)

1 pin TTX_SRES accepts a sync reset input (SRES); a HIGH

impulse resets synchronization of the encoder (ﬁrst ﬁeld, ﬁrst

line)

6 - R/W 0 must be programmed with logic 0 to ensure compatibility to

future enhancements

5 to 0 BE[5:0] R/W ending point of burst in clock cycles

1Dh* PAL: BE = 29; strapping pin FSVGC tied to HIGH

1Dh* NTSC: BE = 29; strapping pin FSVGC tied to LOW

Product data sheet Rev. 04 — 18 January 2006 48 of 84

Philips Semiconductors

SAA7102; SAA7103

Digital video encoder

Table 44: Copy generation 0, 1, 2 and CG enable registers, subaddresses 2Ah to 2Ch, bit

description

Legend: * = default value after reset.

Subaddress Bit Symbol Access Value Description

2Ch 7 CGEN R/W copy generation data output

0* disabled

1 enabled

6 to 4 - R/W 0 must be programmed with logic 0 to ensure

compatibility to future enhancements

3 to 0 CG[19:16] R/W - LSBs of the respective bytes are encoded

immediately after run-in, the MSBs of the

respective bytes have to carry the CRCC bits,

in accordance with the deﬁnition of copy

generation management system encoding

format.

2Bh 7 to 0 CG[15:8]

2Ah 7 to 0 CG[7:0]

Table 45: Output port control register, subaddress 2Dh, bit description

Legend: * = default value after reset.

Bit Symbol Access Value Description

7 VBSEN R/W pin GREEN_VBS_CVBS provides a

0 component GREEN signal (CVBSEN1 = 0) or CVBS signal

(CVBSEN1 = 1)

1* luminance (VBS) signal

6 CVBSEN1 R/W pin GREEN_VBS_CVBS provides a

0* component GREEN (G) or luminance (VBS) signal

1 CVBS signal

5 CVBSEN0 R/W pin BLUE_CB_CVBS provides a

0 component BLUE (B) or color difference BLUE (C

) signal

1* CVBS signal

4 CEN R/W pin RED_CR_C provides a

0 component RED (R) or color difference RED (C

) signal

1* chrominance signal (C) as modulated subcarrier for

S-video

3 ENCOFF R/W encoder

0* active

1 bypass, DACs are provided with RGB signal after cursor

insertion block

2 CLK2EN R/W pin TTXRQ_XCLKO2 provides

0 teletext request signal (TTXRQ)

1* buffered crystal clock divided by two (13.5 MHz)

1 and 0 - R/W 0 must be programmed with logic 0 to ensure compatibility to

future enhancements

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SAA7103H/V4,518

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Manufacturer:

NXP Semiconductors

Description:

IC DIGITAL VIDEO ENCODER 44QFP

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SAA7103H/V4,518

SAA7103H/V4,518

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