15©2018 Integrated Device Technology, Inc. March 15, 2018
5P49V6965 Datasheet
Features and Functional Blocks
Device Startup and Power-On-Reset
The device has an internal power-up reset (POR) circuit. All V
DD
s
must be connected to desired supply voltage to trigger POR.
User can define specific default configurations through internal
One-Time-Programmable (OTP) memory. Either customer or
factory can program the default configuration. Please refer to
VersaClock 6E Family Register Descriptions and Programming
Guide for details or contact IDT if a specific factory-programmed
default configuration is required.
Device will identity which of the 2 modes to operate in by the state
of OUT0_SEL_I2CB pin at POR. Both of the 2 modes default
configurations can be programmed as stated above.
1. Software Mode (I
2
C): OUT0_SEL_I2CB is low at POR.
I
2
C interface will be open to users for in-system programming,
overriding device default configurations at any time.
2. Hardware Select Mode: OUT0_SEL_I2CB is high at POR.
Device has been programmed to load OTP at power-up
(REG0[7]=1). The device will load internal registers according
to Table 18.
Internal OTP memory can support up to 4 configurations,
selectable by SEL0/SEL1 pins.
At POR, logic levels at SEL0 and SEL1 pins must be settled,
resulting the selected configuration to be loaded at power up.
After the first 10ms of operation, the levels of the SELx pins
can be changed, either to low or to the same level as
V
DDD
/V
DDA
. The SELx pins must be driven with a digital signal
of < 300ns rise/fall time and only a single pin can be changed
at a time. After a pin level change, the device must not be
interrupted for at least 1ms so that the new values have time to
load and take effect.
Reference Clock and Selection
The device supports up to two clock inputs.
▪ Crystal input, can be driven by a single-ended clock.
▪ Clock input (CLKIN, CLKINB), a fully differential input that only
accepts a reference clock. A single-ended clock can also drive
it on CLKIN.
Figure 7. Clock Input Diagram, Internal Logic
Manual Switchover
The CLKSEL pin selects the input clock between either XTAL/REF
or (CLKIN, CLKINB). CLKSEL polarity can be changed by I
2
C
programming (Byte 0x13[1]) as shown in the table below.
0 = XIN/REF, XOUT (default); 1 = CLKIN, CLKINB.
When SM[1:0] is “0x”, the redundant inputs are in manual
switchover mode. In this mode, CLKSEL pin is used to switch
between the primary and secondary clock sources. The PRIMSRC
bit determines the primary and secondary clock source setting.
During the switchover, no glitches will occur at the output of the
device, although there may be frequency and phase drift,
depending on the exact phase and frequency relationship
between the primary and secondary clocks.
Table 18. Power-up Behavior
OUT0_SEL_I2CB
at POR
SEL1 SEL0
I
2
C
Access
REG0:7 Config
100No00
101No01
110No02
111No03
0XXYes1
I
2
C
defaults
0XXYes00
Table 19. Input Clock Select
PRIMSRC
(Register 0x13[1])
CLKSEL Source
0 0 XIN/REF
0 1 CLKIN, CLKINB
1 0 CLKIN, CLKINB
1 1 XIN/REF
XIN/REF
XOUT
CLKIN
CLKINB
CLKSEL
OTP
and
Control
Logic
PRIMSRC
Reg 0x13[1]
