21©2018 Integrated Device Technology, Inc. March 15, 2018
5P49V6965 Datasheet
Wiring the CLKIN Pin to Accept Single-ended Inputs
CLKIN cannot take a signal larger than 1.2V pk-pk due to the 1.2V regulated input inside. However, it is internally AC coupled so it is able
to accept both LVDS and LVPECL input signals.
Occasionally, it is desired to have CLKIN to take CMOS levels. Below is an example showing how this can be achieved.
This configuration has three properties:
1. Total output impedance of Ro and Rs matches the 50Ω transmission line impedance.
2. Vrx voltage is generated at the CLKIN which maintains the LVCMOS driver voltage level across the transmission line for best S/N.
3. R1–R2 voltage divider values ensure that Vrx p-p at CLKIN is less than the maximum value of 1.2V.
Figure 12. Recommended Schematic for Driving CLKIN with LVCMOS Driver
Table 24 shows resistor values that ensure the maximum drive level for the CLKIN port is not exceeded for all combinations of 5%
tolerance on the driver V
DD
, V
DDO0
and 5% resistor tolerances. The values of the resistors can be adjusted to reduce the loading for
slower and weaker LVCMOS driver by increasing the impedance of the R1–R2 divider. To better assist this assessment, the total load
(Ro + Rs + R1 + R2) on the driver is included in the table.
Driving CLKIN with Differential Clock
CLKIN/CLKINB will accept DC coupled HCSL/LVPECL/LVDS signals.
Figure 13. CLKIN, CLKINB Input Driven by an HCSL Driver
Table 24. Nominal Voltage Divider Values for Overdriving CLKIN with Single-ended Driver
LVCMOS Diver V
DD
Ro + Rs R1 R2 Vrx (peak) Ro+Rs+R1+R2
3.3 50.0 130 75 0.97 255
2.5 50.0100 1001.00250
1.8 50.0 62 130 0.97 242
R1
R2
Vrx
Vers aCloc k 5 Rec eiver
CLKIN
CLKINB
LVCMOS
VDD
Zo = 50 Ohm
Ro + Rs = 50
Rs
Ro
Zo=50ohm
Zo=50ohm
CLKIN
CLKINB
VersaClock 6 Receiver
Q
nQ
