17©2018 Integrated Device Technology, Inc. March 15, 2018
5P49V6965 Datasheet
Programmable Loop Filter
Fractional Output Dividers (FOD)
The device has 4 fractional output dividers (FOD). Each of the
FODs are comprised of a 12-bit integer counter, and a 24-bit
fractional counter. The output divider can operate in integer divide
only mode for improved performance, or utilize the fractional
counters to generate a clock frequency accurate to 50ppb.
FOD has the following features:
Individual Spread Spectrum Modulation
The output clock frequencies can be modulated to spread energy
across a broader range of frequencies, lowering system EMI.
Each divider has individual spread ability. Spread modulation
independent of output frequency, a triangle wave modulation
between 30 and 63kHz.
Spread spectrum can be applied to any output clock, any clock
frequency, and any spread amount from ±0.25% to ±2.5%
center-spread and -0.5% to -5% down-spread.
Bypass Mode
Bypass mode (divide by 1) to allow the output to behave as a
buffered copy from the input or another FOD.
Cascaded Mode
As shown in the block diagram, FODs can be cascaded for lower
output frequency.
For example, user currently has OUT1 running at 12.288MHz and
needs another 48kHz output. The user can cascade FOD2 by
taking input from OUT1, with a divide ratio of 256. In this way,
OUT 2 is running at 48kHz while in alignment with 12.288MHz on
OUT1.
Dividers Alignment
Each output divider block has a synchronizing pulse to provide
startup alignment between outputs dividers. This allows alignment
of outputs for low skew performance.
When device is at hardware select mode outputs will be
automatically aligned at POR. The same synchronization reset is
also triggered when switching between configurations with the
SEL0/1 pins. This ensures that the outputs remain aligned in
every configuration.
When using software mode I
2
C to reprogram an output divider
during operation, alignment can be lost. Alignment can be
restored by manually triggering the reset through I
2
C.
The outputs are aligned on the falling edges of each output by
default. Rising edge alignment can also be achieved by utilizing
the programmable skew feature to delay the faster clock by 180
degrees. The programmable skew feature also allows for fine
tuning of the alignment.
Programmable Skew
The device has the ability to skew outputs by quadrature values.
The skew on each output can be adjusted from 0 to 360 degrees.
Skew is adjusted in units equal to 1/32 of the VCO period. So, for
100MHz output and a 2800MHz VCO, you can select how many
11.161ps units you want added to your skew (resulting in units of
0.402 degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and
so on. The granularity of the skew adjustment is always
dependent on the VCO period and the output period.
Output Drivers
The device output drivers support the following features
individually:
▪ 2.5V or 3.3V voltage level for HCSL/LVPECL operation
▪ 1.8V, 2.5V or 3.3V voltage levels for CMOS/LVDS operation
▪ CMOS supports 4 operating modes:
— CMOSD: OUTx and OUTxB 180 degrees out of phase
— CMOSX2: OUTx and OUTxB phase-aligned
— CMOS1: only OUTx pin is on
— CMOS2: only OUTxB pin is on
When a given output is configured to at CMOSD or CMOSX2, then
all previously described configuration and control apply equally to
both pins.
▪ Independent output enable/disabled by register bits. When
disabled, an output can be either in a logic 1 state or Hi-Z.
The following options are used to disable outputs:
1. Output turned off by I
2
C.
2. Output turned off by SD/OE pin.
3. Output unused, which means is turned off regardless of OE pin
status.
Table 22. Loop Filter
The device PLL loop bandwidth range depends on the input
reference frequency (Fref).
Input Reference
Frequency (MHz)
Loop Bandwidth
Minimum (kHz)
Loop Bandwidth
Maximum (kHz)
140126
350 300 1000
