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5P49V6965A000NLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
7©2018 Integrated Device Technology, Inc. March 15, 2018
5P49V6965 Datasheet
1
Practical lower frequency is determined by loop filter settings.
2
A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3
Duty cycle is only guaranteed at maximum slew rate settings.
4
Actual PLL lock time depends on the loop configuration.
5
Includes loading the configuration bits from EPROM to PLL registers. It does not include EPROM programming/write time.
6
Power-up with temperature calibration enabled; contact IDT if shorter lock-time is required in system.
Table 6. General AC Timing Characteristics
V
DDA
, V
DDD
, V
DDO0
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, T
A
= -40°C to +85°C unless stated otherwise.
Symbol Parameter Conditions Minimum Typical Maximum Units
F
IN
1
Input Frequency
Input frequency limit (crystal). 8 40 MHz
Input frequency limit (CLKIN,CLKINB). 1 350 MHz
Input frequency limit (single-ended over
XIN).
1200MHz
F
OUT
2
Output Frequency
Single-ended clock output limit (LVCMOS),
individual FOD mode.
1200
MHz
Differential clock output limit
(LVPECL/LVDS/HCSL), individual FOD
mode.
1350
Single-ended clock output limit (LVCMOS),
cascaded FOD mode, output 2–4.
0.001 200
Differential clock output limit
(LVPECL/LVDS/HCSL), cascaded FOD
mode, output 2–4.
0.001 350
f
VCO
VCO Operating Frequency
Range
2500 2900 MHz
T
DC
3
Output Duty Cycle
Measured at V
DD
/2, all outputs except
reference output, V
DDOX
= 2.5V or 3.3V.
45 50 55 %
Measured at V
DD
/2, all outputs except
reference output, V
DDOX
= 1.8V
40 50 60 %
Measured at V
DD
/2, reference output OUT0
(5MHz–150.1MHz) with 50% duty cycle
input.
40 50 60 %
Measured at V
DD
/2, reference output OUT0
(150.1MHz–200MHz) with 50% duty cycle
input.
30 50 70 %
T
SKEW
Output Skew
Skew between the same frequencies, with
outputs using the same driver format and
phase delay set to 0ns.
75 ps
T
STARTUP
4,5
Startup Time
Measured after all V
DD
s have risen above
90% of their target value
6
.
30 ms
PLL lock time from shutdown mode. 3 4 ms
8©2018 Integrated Device Technology, Inc. March 15, 2018
5P49V6965 Datasheet
Table 7. General Input Characteristics
V
DDA
, V
DDD
, V
DDO0
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, T
A
= -40°C to +85°C unless stated otherwise.
Symbol Parameter Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance
CLKIN,CLKINB,CLKSEL,SD/OE,SEL1/S
DA, SEL0/SCL
37pF
R
PD
Pull-down Resistor
CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL,
CLKIN, CLKINB, OUT0_SEL_I2CB
100 300 kΩ
V
IH
Input High Voltage CLKSEL, SD/OE. 0.7 x V
DDD
V
DDD
+ 0.3 V
V
IL
Input Low Voltage CLKSEL, SD/OE. GND - 0.3 0.3 x V
DDD
V
V
IH
Input High Voltage OUT0_SEL_I2CB. 1.7 V
DDO0
+ 0.3 V
V
IL
Input Low Voltage OUT0_SEL_I2CB. GND - 0.3 0.4 V
V
IH
Input High Voltage XIN/REF. 0.8 1.2 V
V
IL
Input Low Voltage XIN/REF. GND - 0.3 0.4 V
T
R
/T
F
Input Rise/Fall Time CLKSEL, SD/OE, SEL1/SDA, SEL0/SCL. 300 ns
Table 8. CLKIN Electrical Characteristics
V
DDA
, V
DDD
, V
DDO0
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, T
A
= -40°C to +85°C unless stated otherwise.
Symbol Parameter Conditions Minimum Typical Maximum Units
V
SWING
Input Amplitude – CLKIN, CLKINB Peak to peak value, single-ended. 200 1200 mV
dv/dt Input Slew Rate – CLKIN, CLKINB Measured differentially. 0.4 8 V/ns
I
IL
Input Leakage Low Current V
IN
= GND. -5 5 μA
I
IH
Input Leakage High Current V
IN
= 1.7V. 20 μA
DC
IN
Input Duty Cycle
Measurement from differential
waveform.
45 55 %
9©2018 Integrated Device Technology, Inc. March 15, 2018
5P49V6965 Datasheet
Table 9. Electrical Characteristics – CMOS Outputs
V
DDA
, V
DDD
, V
DDO0
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, T
A
= -40°C to +85°C unless stated otherwise.
Symbol Parameter Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage I
OH
= -15mA (3.3V), -12mA (2.5V), -8mA (1.8V). 0.7 x V
DDO
V
DDO
V
V
OL
Output Low Voltage I
OL
= 15mA (3.3V), 12mA (2.5V), 8mA (1.8V). 0.4 V
R
OUT
Output Driver Impedance CMOS output driver. 17 Ω
T
SR
Slew Rate, SLEW[1:0] = 00
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of V
DDO
(output load
= 5pF) V
DDOX
= 3.3V.
1.0 2.2
V/ns
Slew Rate, SLEW[1:0] = 01 1.2 2.3
Slew Rate, SLEW[1:0] = 10 1.3 2.4
Slew Rate, SLEW[1:0] = 11 1.7 2.7
Slew Rate, SLEW[1:0] = 00
Single-ended 2.5V LVCMOS output clock rise
and fall time, 20% to 80% of V
DDO
(output load
= 5pF) V
DDOX
= 2.5V.
0.6 1.3
Slew Rate, SLEW[1:0] = 01 0.7 1.4
Slew Rate, SLEW[1:0] = 10 0.6 1.4
Slew Rate, SLEW[1:0] = 11 1.0 1.7
Slew Rate, SLEW[1:0] = 00
Single-ended 1.8V LVCMOS output clock rise
and fall time, 20% to 80% of V
DDO
(output load
= 5pF) V
DD
= 1.8V.
0.3 0.7
Slew Rate, SLEW[1:0] = 01 0.4 0.8
Slew Rate, SLEW[1:0] = 10 0.4 0.9
Slew Rate, SLEW[1:0] = 11 0.7 1.2
I
OZDD
Output Leakage Current
(OUT1–4)
Tri-state outputs. 5 μA
Output Leakage Current (OUT0) Tri-state outputs. 30 μA
Table 10. Electrical Characteristics – LVDS Outputs
V
DDA
, V
DDD
, V
DDO0
= 3.3V ±5%, 2.5V ±5%, 1.8V ±5%, T
A
= -40°C to +85°C unless stated otherwise.
Symbol Parameter Minimum Typical Maximum Units
V
OT
(+) Differential Output Voltage for the TRUE Binary State 247 454 mV
V
OT
(-) Differential Output Voltage for the FALSE Binary State -454 -247 mV
ΔV
OT
Change in V
OT
between Complimentary Output States 50 mV
V
OS
Output Common Mode Voltage (Offset Voltage) at 3.3 V ±5%, 2.5V ±5% 1.125 1.25 1.375 V
Output Common Mode Voltage (Offset Voltage) at 1.8V ±5% 0.8 0.875 0.96 V
ΔV
OS
Change in V
OS
between Complimentary Output States 50 mV
I
OS
Outputs Short Circuit Current, V
OUT
+ or V
OUT
- = 0V or V
DDO
924mA
I
OSD
Differential Outputs Short Circuit Current, V
OUT
+ = V
OUT
-612mA
T
R
LVDS rise time 20%–80% 300 ps
T
F
LVDS fall time 80%–20% 300 ps
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5P49V6965A000NLGI

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