22©2018 Integrated Device Technology, Inc. March 15, 2018
5P49V6965 Datasheet
Output – Single-ended or Differential Clock Terminations
LVDS Termination
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value
should be selected to match the differential impedance (Zo) of your transmission line. A typical point-to-point LVDS design uses a 100
parallel resistor at the receiver and a 100. differential transmission-line environment. In order to avoid any transmission-line reflection
issues, the components should be surface mounted and must be placed as close to the receiver as possible. The standard termination
schematic as shown in figure Standard Termination or the termination of figure Optional Termination can be used, which uses a center tap
capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. In addition, since these outputs are
LVDS compatible, the input receiver's amplitude and common-mode input range should be verified for compatibility with the IDT LVDS
output. If using a non-standard termination, it is recommended to contact IDT and confirm that the termination will function as intended.
For example, the LVDS outputs cannot be AC coupled by placing capacitors between the LVDS outputs and the 100 shunt load. If AC
coupling is required, the coupling caps must be placed between the 100 shunt termination and the receiver. In this manner the
termination of the LVDS output remains DC coupled.
Figure 14. Standard and Optional Terminations
LVDS
Driver
LVDS
Driver
LVDS
Receiver
LVDS
Receiver
Z
T
C
Z
O
Z
T
Z
O
Z
T
Z
T
2
Z
T
2
Standard Termination
Optional Termination
23©2018 Integrated Device Technology, Inc. March 15, 2018
5P49V6965 Datasheet
LVPECL Termination
The clock layout topology shown below is a typical termination for LVPECL outputs.
The differential outputs generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or
current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance
techniques should be used to maximize operating frequency and minimize signal distortion.
For V
DDO
= 2.5V, the V
DDO
- 2V is very close to ground level. The R3 in 2.5V LVPECL output termination can be eliminated and the
termination is shown in Figure 18, 2.5V LVPECL Output Termination (3).
Figure 15. 3.3V LVPECL Output Termination (1)
Figure 16. 3.3V LVPECL Output Termination (2)
Figure 17. 2.5V LVPECL Output Termination (3)
Figure 18. 2.5V LVPECL Driver Termination (2)
Figure 19. 2.5V LVPECL Driver Termination (3)
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R1 R2
3.3V
50 Ohm
50 Ohm
RTT
50 Ohm
Input
+
-
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
+
-
Input
R1 R2
3.3V
84 Ohm
84 Ohm
3.3V
R3 R4
125 Ohm
125 Ohm
2.5V LVPECL
Driver
Zo = 50 Ohm
Zo = 50 Ohm
2.5V
+
-
R2 R4
V
DDO
= 2.5V
62.5 Ohm
62.5 Ohm
2.5V
R1 R3
250 Ohm
250 Ohm
2.5V LVPECL
Driver
Zo = 50 Ohm
Zo = 50 Ohm
2.5V
+
-
R1 R2
V
DDO
= 2.5V
50 Ohm
50 Ohm
2.5V LVPECL
Driver
Zo = 50 Ohm
Zo = 50 Ohm
2.5V
+
-
R1 R2
V
DDO
= 2.5V
50 Ohm
50 Ohm
R3
18 Ohm
24©2018 Integrated Device Technology, Inc. March 15, 2018
5P49V6965 Datasheet
HCSL Termination
HCSL termination scheme applies to both 3.3V and 2.5V V
DDO
.
Figure 20. HCSL Receiver Terminated
Figure 21. HCSL Source Terminated
50 Ohm
HCSL
Zo = 50 Ohm
Zo = 50 Ohm
+
-
50 Ohm
VersaClock 6+ Output
Driver
Receiver
33 Ohm
33 Ohm
HCSL
+
-
VersaClock 6+ Output
Driver
Receiver
Zo = 50 Ohm
Zo = 50 Ohm
50 Ohm
50 Ohm
33 Ohm
33 Ohm

5P49V6965A000NLGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products VersaClock 6E Standard Part
Lifecycle:
New from this manufacturer.
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