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P80C557E4EFB/01,55

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
1999 Mar 02
25
Figure 22. T2 control register (TM2CON).
76543210
TM2CON (EAH) T2IS1 T2IS0 T2ER T2BO T2P1 T2P0 T2MS1 T2MS0
Table 15. Description of TM2CON bits
SYMBOL BIT FUNCTION
T2IS1 TM2CON.7 Timer T2 16-bit overflow interrupt select
T2IS0 TM2CON.6 Timer T2 byte overflow interrupt select
T2ER TM2CON.5 Timer T2 external reset enable. When this bit is set, Timer T2 may be reset by a rising edge on RT2 (P1.5).
T2BO TM2CON.4 Timer T2 byte overflow interrupt flag
T2P1 TM2CON.3 Timer T2 prescaler select
T2P0 TM2CON.2
T2MS1 TM2CON.1 Timer T2 mode select
T2MS0 TM2CON.0
Table 16. Timer 2 prescaler select
T2P1 T2P0 TIMER T2 CLOCK
0 0 Clock source
0 1 Clock source/2
1 0 Clock source/4
1 1 Clock source/8
Table 17. Timer 2 mode select
T2MS1 T2MS0 MODE SELECTED
0 0 Timer T2 halted (off)
0 1 T2 clock source = f
CLK
/12
1 0 Test mode; do not use
1 1 T2 clock source = pin T2
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
1999 Mar 02
26
Figure 23. Capture control register (CTCON).
76543210
CTCON (EBH) CTN3 CTP3 CTN2 CTP2 CTN1 CTP1 CTN0 CTP0
Table 18. Description of CTCON bits
SYMBOL BIT FUNCTION
CTN3 CTCON.7 Capture Register 3 triggered by a falling edge on CT3I
CTP3 CTCON.6 Capture Register 3 triggered by a rising edge on CT3I
CTN2 CTCON.5 Capture Register 2 triggered by a falling edge on CT2I
CTP2 CTCON.4 Capture Register 2 triggered by a rising edge on CT2I
CTN1 CTCON.3 Capture Register 1 triggered by a falling edge on CT1I
CTP1 CTCON.2 Capture Register 1 triggered by a rising edge on CT1I
CTN0 CTCON.1 Capture Register 0 triggered by a falling edge on CT0I
CTP0 CTCON.0 Capture Register 0 triggered by a rising edge on CT0I
The contents of the Compare Registers CM0, CM1 and CM2 are
continuously compared with the counter value of Timer T2. When a
match occurs, an interrupt may be invoked. A match of CM0 sets
the bits 0–5 of Port 4, a CM1 match resets these bits and a CM2
match toggles bits 6 and 7 of Port 4, provided these functions are
enabled by the STE respectively RTE registers. A match of CM0
and CM1 at the same time results in resetting bits 0–5 of Port 4.
CM0, CM1 and CM2 are reset by the RSTIN signal.
Figure 24. Interrupt flag register (TM2IR).
76543210
TM2IR (C8H) T2OV CMI2 CMI1 CMI0 CTI3 CTI2 CTI1 CTI0
Table 19. Description of TM2IR bits
SYMBOL BIT FUNCTION
T2OV TM2IR.7 Timer T2 16-bit overflow interrupt flag
CMI2 TM2IR.6 CM2 interrupt flag
CMI1 TM2IR.5 CM1 interrupt flag
CMI0 TM2IR.4 CM0 interrupt flag
CTI3 TM2IR.3 CT3 interrupt flag
CTI2 TM2IR.2 CT2 interrupt flag
CTI1 TM2IR.1 CT1 interrupt flag
CTI0 TM2IR.0 CT0 interrupt flag
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
1999 Mar 02
27
Figure 25. Set enable register (STE).
76543210
STE (EEH) TG47 TG46 SP45 SP44 SP43 SP42 SP41 SP40
Table 20. Description of STE bits
SYMBOL BIT FUNCTION
TG47 STE.7 If “1” then P4.7 is reset on the next toggle, if LOW P4.7 is set on the next toggle
TG46 STE.6 If “1” then P4.6 is reset on the next toggle, if LOW P4.6 is set on the next toggle
SP45 STE.5 If “1” then P4.5 is set on a match between CM0 and Timer T2
SP44 STE.4 If “1” then P4.4 is set on a match between CM0 and Timer T2
SP43 STE.3 If “1” then P4.3 is set on a match between CM0 and Timer T2
SP42 STE.2 If “1” then P4.2 is set on a match between CM0 and Timer T2
SP41 STE.1 If “1” then P4.1 is set on a match between CM0 and Timer T2
SP40 STE.0 If “1” then P4.0 is set on a match between CM0 and Timer T2
Figure 26. Reset/Toggle enable register (RTE).
76543210
RTE (EFH) TP47 TP46 RP45 RP44 RP43 RP42 RP41 RP40
Table 21. Description of RTE bits
SYMBOL BIT FUNCTION
TP47 RTE.7 If “1” then P4.7 toggles on a match between CM2 and Timer T2
TP46 RTE.6 If “1” then P4.6 toggles on a match between CM2 and Timer T2
RP45 RTE.5 If “1” then P4.5 toggles on a match between CM1 and Timer T2
RP44 RTE.4 If “1” then P4.4 toggles on a match between CM1 and Timer T2
RP43 RTE.3 If “1” then P4.3 toggles on a match between CM1 and Timer T2
RP42 RTE.2 If “1” then P4.2 toggles on a match between CM1 and Timer T2
RP41 RTE.1 If “1” then P4.1 toggles on a match between CM1 and Timer T2
RP40 RTE.0 If “1” then P4.0 toggles on a match between CM1 and Timer T2
For more information concerning the TM2CON, CTCON, TM2IR and
the STE/RTE registers see IC20 handbook, chapter “80C51 family
hardware description”.
Port 4 can be read and written by software without affecting the
toggle, set and reset signals. At a byte overflow of the least
significant byte, or at a 16-bit overflow of the timer/counter, an
interrupt sharing the same interrupt vector is requested. Either one
or both of these overflows can be programmed to request an
interrupt.
All interrupt flags must be reset by software.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72

P80C557E4EFB/01,55

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Buy P80C557E4EFB/01,55
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT ROMLESS 80QFP
Lifecycle:
New from this manufacturer.
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