P80C557E4EFB/01,55 Datasheet P80C557E4EFB/01,55, P80C557E4EFB/01,51 | P43-P45

Philips Semiconductors Product specification

P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller

1999 Mar 02

6.11.3 Power-down Mode

The instruction that sets PCON.1 is the last executed prior to going

into the Power-down Mode. Once in Power-down Mode, the HF

oscillator is stopped. The 32 kHz oscillator may stay running. The

content of the on-chip RAM and the Special Function Registers are

preserved. Note that the Power-down Mode can not be entered

when the watchdog has been enabled.

The Power-down Mode can be terminated by an external RESET in

the same way as in the 80C51 (RAM is saved, but SFRs are cleared

due to RESET) or in addition by any one of the external interrupts

(INT0

, INT1) or Seconds interrupt.

The status of the external pins during Power-down Mode is shown in

Table 40. If the Power-down Mode is activated while in external

program memory, the port data that is held in the Special Function

If the data is a logic1, the port pin is held HIGH during the

Power-down Mode by the strong pull-up transistor P1 (see Figure 9).

The Power-down Mode should not be entered within an interrupt

routine because Wake-up with an external or ‘Seconds’ interrupt is

not possible in that case.

6.11.4 Wake-up from Power-down Mode

The Power-down Mode of the P8xC557E4 can also be terminated

by any one of the three enabled interrupts, INT0

, INT1 or Seconds

interrupt.

If there is an interrupt already in service, which has same or higher

priority as the Wake-up interrupt, Power-down Mode will switch over

to Idle Mode and stay there until an interrupt of higher priority

terminates Idle Mode.

A termination with these interrupts does not affect the internal data

memory and does not affect the Special Function Registers. This

gives the possibility to exit Power-down without changing the port

output levels. To terminate the Power-down Mode with an external

interrupt, INT0

or INT1 must be switched to be level-sensitive and

must be enabled. The external interrupt input signal INT0

or INT1

must be kept LOW till the oscillator has restarted and stabilized (see

Figure 41). A Seconds interrupt will terminate the Power-down Mode

if it is enabled and INT1 is level sensitive. In order to prevent any

interrupt priority problems during Wake-up, the priority of the desired

Wake-up interrupt should be higher than the priorities of all other

enabled interrupt sources.

The instruction following the one that put the device into the

Power-down Mode will be the first one which will be executed after

the interrupt routine has been serviced.

6.12 Oscillator Circuits

The input signal SELXTAL1 connected to logic “1” selects the

XTAL1, 2 oscillator (standard 80C51) instead of the XTAL3, 4

oscillator, which is halted and XTAL3, 4 must not be connected.

6.12.1 XTAL1, 2 Oscillator circuit (standard 80C51)

The oscillator circuit of the P8xC557E4 is a single-stage inverting

amplifier in a Pierce oscillator configuration. The circuitry between

the XTAL1 and XTAL2 is basically an inverter biased to the transfer

point. Either a crystal or ceramic resonator can be used as the

feedback element to complete the oscillator circuitry. Both are

operated in parallel resonance. XTAL1 is the high gain amplifier

input, and XTAL2 is the output (see Figure 42). To drive the

P8xC557E4 externally, XTAL1 is driven from an external source and

XTAL2 left open-circuit (see Figure 43).

6.12.2 XTAL3, 4 Circuitry

Please refer to chapter 6.13.1

Figure 42. Using the On-Chip Oscillator.

Quartz crystal

or ceramic

resonator

XTAL1

XTAL2

C1 = C2 = 20pF

External

clock

signal

XTAL2

XTAL1

Figure 43. Using an external clock.

SELXTAL11

SELXTAL1

(NC)

Philips Semiconductors Product specification

P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller

1999 Mar 02

6.13 32kHz PLL Oscillator with Seconds Timer

6.13.1 XTAL3,4 Oscillator Circuitry

The input signal SELXTAL1 connected to logic “0” selects the 32kHz

oscillator together with the PLL instead of the XTAL1,2 oscillator,

which is halted. XTAL2 is floating in that case.

The 32kHz oscillator consists of an inverter, which forms a Pierce

oscillator with the on-chip components C1,C2,Rf and an external

crystal of 32768 Hz.

During the following situations, the inverter is switched to tristate and

XTAL3 is pulled to Vss :

• during Power-down Mode, when the PLL control register bit

RUN32 (PLLCON.7) was set to ’0’;

• during Reset (RSTIN = HIGH) ;

• when the XTAL1,2 oscillator is selected (SELXTAL1 = HIGH).

6.13.2 PLL CCO

A current controlled oscillator (CCO) generates a clock frequency

CCO

of approx. 32 , 38 , 44 or 50 MHz , controlled by the PLL, with

the 32kHz oscillator as the reference clock. The system clock

frequency f

CLK

can be varied under software control by changing the

contents of the PLL control register (PLLCON):

CCO

can be changed via the PLLCON bits FSEL(1:0) (see

Table 41). The maximum locking time is 10 ms

During the stabilization phase, no time critical routines should be

executed.

The system clock frequency f

CLK

is derived from f

CCO

under control

of the PLLCON bits FSEL(4:0) (see Table 41).

If only FSEL(4:2) is changed but not FSEL(1:0), then it takes about

1us until the new frequency is available.

Changing the system clock frequency has to be done in two steps.

From HIGH to LOW frequencies:

First change (FSEL(4:2), then FSEL (1:0).

From LOW to HIGH frequencies:

First change only FSEL (1:0) and after a stabilization phase of

10 ms change FSEL (4:2).

6.13.3 PLL Control Register – PLLCON

PLLCON is a special function register, which can be read and

written by software. It contains the control bits:

• to select one of several system clock frequencies (see Table 41);

• the seconds interrupt flag: SECINT

• to enable the seconds interrupt flag: ENSECI

• the RUN32 bit, which defines if during Power-down Mode the

32kHz oscillator is halted or stays running.

PLLCON is initialized to 0DH upon Reset (RSTIN = ‘1’) or Watchdog

Timer Overflow. PLLCON = 0DH corresponds to a system clock

frequency of 11.01 MHz.

Figure 44. PLL control register (PLLCON).

76543210

PLLCON (F9H) RUN32 ENSECI SECINT FSEL.4 FSEL.3 FSEL.2 FSEL.1 FSEL.0

Table 41. PLLCON

SYMBOL BIT FUNCTION

RUN32 PLLCON.7 RUN32 = 0: The 32 kHz oscillator halts during Power-down.

RUN32 = 1: The 32 kHz oscillator stays running during Power-down.

ENSECI PLLCON.6 Enable the seconds interrupt. (enabling INT1 is also required)

SECINT PLLCON.5 Seconds interrupt requested by an overflow of the seconds timer (which occurs every second) or via writing

a ‘1’ to this bit. SECINT can only be cleared by writing a ’0’ to this bit .

FSEL.4 PLLCON.4 System clock frequency in MHz

FSEL.0

PLLCON.0

FSEL[1:0] 10

15.73

7.86

9.44

11.01

12.58

3.93

4.72

5.51

6.29

010011100

FSEL[4:2]

Other combinations, than mentioned above, are reserved and may not be selected. This allows to generate the standard baudrates 19200,

9600, 4800, 2400 and 1200 Baud, when using the UART and Timer1.

NOTE:

1. This parameter is characterized.

Philips Semiconductors Product specification

P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller

1999 Mar 02

6.13.4 Seconds Timer

This counter provides an overflow signal every second, when the

32kHz oscillator is running.

The overflow output sets the interrupt flag SECINT. This interrupt

can be disabled/enabled by ENSECI. If SECINT is enabled, it is

logically ORed with INT1 (external interrupt 1).

Seconds interrupt and INT1 therefor share the same priority and

vector. The software has to check both flags SECINT (PLLCON.5)

and IE1 (TCON.3), to distinguish between the two interrupt sources.

SECINT can only be cleared via writing a ‘0’ to this bit .

The external interrupts INT0 , INT1 or the seconds interrupt can

Wake-up the PLL oscillator and the microcontroller as described in

chapter “Wake-up from Power-down Mode”.

For a Wake-up via INT1 or seconds interrupt, IE1 must be enabled

and level-sensitive.

A further function of the seconds timer is to control the start-up

timing of the microcontroller after Reset or after Wake-up from

Power-down. It controls the stretching of the reset pulse to the

microcontroller and controls releasing the system clock to the

microcontroller.

A RSTIN signal of 1us at minimum will reset the microcontroller.

In case of Reset or Wake-up with halted 32kHz oscillator: From

RSTIN falling edge or Wake-up interrupt it takes 560ms at maximum

for the start-up of the 32kHz oscillator itself and the stabilization of

the PLL’s.

In case of Wake-up with running 32kHz oscillator: From Wake-up

interrupt it takes about 1ms for the stabilization of the PLL’s.

After this start-up time, the microcontroller is supplied with the

system clock and – in case of a reset – the internally

stretched reset

signal overlaps about 45us, to guarantee a proper initialization of the

microcontroller.

For further information refer to section

6.11 Power reduction modes

XTAL3

Figure 45. Block diagram PLL

Oscil-

lator

32.768 KHz

32 kHz

Phase

comparator

Loop

filter

CCO

Internal Bus

SECONDS TIMER

PLLCON

RSTIN

Programmable

divider system clock

Reset to controller

’Seconds’

Interrupt

request

PD = power down

Stretched

Reset

RUN32 PD

XTAL4

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P80C557E4EFB/01,55

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IC MCU 8BIT ROMLESS 80QFP

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