Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
1999 Mar 02
65
11. AC CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
V
DD
= 5 V ± 10% (EBx), V
SS
= 0 V, t
CLK
min = 1/fmax (maximum operating frequency)
V
DD
= 5 V ± 10% (EFx), V
SS
= 0 V, t
CLK
min = 1/fmax (maximum operating frequency)
T
amb
= 0 °C to +70 °C, t
CLK
min = 63 ns for P8xC557E4EBx
T
amb
= –40 °C to +85 °C, t
CLK
min = 63 ns for P8xC557E4EFx
C1 = 100 pF for Port 0, ALE and PSEN
; C1 = 80 pF for all other outputs unless otherwise specified.
12MHz CLOCK 16MHz CLOCK VARIABLE CLOCK
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX MIN MAX UNIT
1/t
CLK
60 System clock frequency 3.5 16 MHz
t
LHLL
60 ALE pulse width 127 85 2t
CLK
–40 ns
t
AVLL
60 Address valid to ALE LOW 43 23 t
CLK
–40 ns
t
LLAX
60 Address hold after ALE LOW 53 33 t
CLK
–30 ns
t
LLIV
60 ALE LOW to valid instruction in 234 150 4t
CLK
–100 ns
t
LLPL
60 ALE LOW to PSEN LOW 53 33 t
CLK
–30 ns
t
PLPH
60 PSEN pulse width 205 143 3t
CLK
–45 ns
t
PLIV
60 PSEN LOW to valid instruction in 145 83 3t
CLK
–105 ns
t
PXIX
60 Input instruction hold after PSEN 0 0 0 ns
t
PXIZ
60 Input instruction float after PSEN 59 38 t
CLK
–25 ns
t
AVIV
60 Address to valid instruction in 312 208 5t
CLK
–105 ns
t
PLAZ
60 PSEN LOW to address float 10 10 10 ns
Data Memory
t
AVLL
61, 62 Address valid to ALE LOW 43 23 t
CLK
–40 ns
t
LLAX
61, 62 Address hold after ALE LOW 48 28 t
CLK
–35 ns
t
RLRH
61 RD pulse width 400 275 6t
CLK
–100 ns
t
WLWH
62 WR pulse width 400 275 6t
CLK
–100 ns
t
RLDV
61 RD LOW to valid data in 252 148 5t
CLK
–165 ns
t
RHDX
61 Data hold after RD 0 0 0 ns
t
RHDZ
61 Data float after RD 97 55 2t
CLK
–70 ns
t
LLDV
61 ALE LOW to valid data in 517 350 8t
CLK
–150 ns
t
AVDV
61 Address to valid data in 585 398 9t
CLK
–165 ns
t
LLWL
61, 62 ALE LOW to RD or WR LOW 200 300 138 238 3t
CLK
–50 3t
CLK
+50 ns
t
AVWL
61, 62 Address valid to WR LOW or RD LOW 203 120 4t
CLK
–130 ns
t
QVWX
62 Data valid to WR transition 33 13 t
CLK
–50 ns
t
QVWH
62 Data before WR 433 288 7t
CLK
–150 ns
t
WHQX
62 Data hold after WR 33 13 t
CLK
–50 ns
t
RLAZ
61 RD low to address float 0 0 0 ns
t
WHLH
61, 62 RD or WR HIGH to ALE HIGH 43 123 23 103 t
CLK
–40 t
CLK
+40 ns
UART Timing – Shift Register Mode (Test Conditions: T
amb
= 0 °C to +70 °C; V
SS
= 0 V; Load Capacitance = 80pF)
t
XLXL
64 Serial port clock cycle time 1.0 0.75 12t
CLK
µs
t
QVXH
64 Output data setup to clock rising edge 700 492 10t
CLK
–133 ns
t
XHQX
64 Output data hold after clock rising edge 50 8 2t
CLK
–117 ns
t
XHDX
64 Input data hold after clock rising edge 0 0 0 ns
t
XHDV
64 Clock rising edge to input data valid 700 492 10t
CLK
–133 ns
