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P80C557E4EFB/01,55

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
1999 Mar 02
28
6.8 Watchdog Timer T3
In addition to Timer T2 and the standard timers, a watchdog timer
(T3) consisting of an 11-bit prescaler and an 8-bit timer is also
incorporated (see Figure 27).
The timer is incremented every 1.5 ms, derived from the system
clock frequency of 16 MHz by the following:
f
timer
f
CLK
12 2048
When a timer overflow occurs, the microcontroller is reset and a
reset output pulse is generated at pin RSTOUT. Also the PLL control
register is reset.
To prevent a system reset the timer must be reloaded in time by the
application software. If the processor suffers a hardware/software
malfunction, the software will fail to reload the timer. This failure will
produce a reset upon overflow thus preventing the processor
running out of control.
The watchdog timer can only be reloaded if the condition flag
WLE = PCON.4 has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
The time interval between the timer’s reloading and the occurrence
of a reset depends on the reloaded value. For example, this may
range from 1.5 ms to 0.375 s when using an oscillator frequency of
16 MHz.
In the Idle state the watchdog timer and reset circuitry remain active.
The watchdog timer is controlled by the watchdog enable pin (EW
).
A LOW level enables the watchdog timer and disables the
Power-down Mode. A HIGH level disables the watchdog timer and
enables the Power-down Mode.
Figure 27. Watchdog timer.
Internal Bus
Timer T3
(8-bit)
LOAD LOADEN
Prescaler
(11-bit)
Clear
f
CLK
/12
EW
WLE
Clear
PD
LOADEN
Internal Bus
Write T3
PCON.4
PCON.1
to reset circuitry (see Figure 46)
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
1999 Mar 02
29
6.9 Serial I/O
The P8xC557E4 is equipped with two independent serial ports:
SIO0 and SI01. SIO0 is the full duplex UART port, identical to the
PCB80C51 serial port. SIO1 is an I
2
C-bus serial I/O interface with
byte oriented master and slave functions.
6.9.1 SIO0 (UART)
SIO 0 is a full duplex serial I/O port – it can transmit and receive
simultaneously. This serial port is also receive-buffered. It can
commence reception of a second byte before the previously
received byte has been read from the receive register. If, however,
the first byte has still not been read by the time reception of the
second byte is complete, one of the bytes will be lost. The SIO0
receive and transmit registers are both accessed via the S0BUF
special function register. Writing to S0BUF loads the transmit
register, and reading S0BUF accesses to a physically separate
receive register. SIO0 can operate in 4 modes:
Mode 0: Serial data is transmitted and received through RXD.
TXD outputs the shift clock. 8 data bits are
transmitted/received (LSB first). The baud rate is
fixed at 1/12 of the oscillator frequency. A write into
S0CON should be avoided during a transmission to
avoid spikes on RXD/TXD.
Mode 1: 10 bits are transmitted via TXD or received through
RXD: a start bit (0), 8 data bits (LSB first), and a
stop bit(1). On receive, the stop bit is put into RB8
(S0CON special function register). The baud rate is
variable.
Mode 2: 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On
transmit, the 9th data bit (TB8 in S0CON) can be
assigned the value of 0 or 1. With nominal software,
TB8 can be the parity bit (P in PSW). During a
receive, the 9th data bit is stored in RB8 (S0CON),
and the stop bit is ignored. The baud rate is
programmable to either 1/32 or 1/64 of the oscillator
frequency.
Mode 3: 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). Mode
3 is the same as Mode 2 except the baud rate which
is variable in Mode 3.
In all four modes, transmission is initiated by any instruction that
writes to the S0BUF function register. Reception is initiated in Mode
0 when RI = 0 and REN = 1. In the other three modes, reception is
initiated by the incoming start bit provided that REN = 1.
Modes 2 and 3 are provided for multiprocessor communications. In
these modes, 9 data bits are received with the 9th bit written to RB8.
The 9th bit is followed by the stop bit. The port can be programmed
so that with receiving the stop bit, the serial port interrupt will be
activated if, and only if RB8 = 1.
This feature is enabled by setting bit SM2 in S0CON. This feature
may be used in multiprocessor systems.
For more information about how to use the UART in combination
with the registers S0CON, PCON, IEN0, S0BUF and Timer register
refer to the 80C51 Data Handbook IC20.
Figure 28. Serial port control (S0CON) register.
76543210
S0CON (98H) SM0 SM1 SM2 REN TB8 RB8 TI RI
Table 22. Description of S0CON bits
SYMBOL BIT FUNCTION
SM0 S0CON.7 This bit is used to select the serial port mode. See Table 23.
SM1 S0CON.6 This bit is used to select the serial port mode. See Table 23.
SM2 S0CON.5 Enables the multiprocessor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set to 1, then
RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI will not be activated
if a valid stop bit was not received. In mode 0, SM2 should be 0.
REN S0CON.4 Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8 S0CON.3 The 9th data bit that will be transmitted in modes 2 and 3. Set or clear by software as desired.
RB8 S0CON.2 In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit that was
received. In mode 0, RB8 is not used.
TI S0CON.1 The transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the
stop bit in the other modes, in any serial transmission. Must be cleared by software.
RI S0CON.0 The receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop
bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
Philips Semiconductors Product specification
P83C557E4/P80C557E4/P89C557E4Single-chip 8-bit microcontroller
1999 Mar 02
30
Table 23. Description of S0CON bits
SM0 SM1 MODE DESCRIPTION BAUD RATE
0 0 0 Shift register f
CLK
/12
0 1 1 8-bit UART variable
1 0 2 9-bit UART f
CLK
/64 or f
CLK
/32
1 1 3 9-bit UART variable
6.9.2 SIO1 (I
2
C-bus Interface)
The SIO1 of the P8xC557E4 provides the fast-mode, which allows a
fourthfold increase of the bitrate up to 400 kHz. Nevertheless it is
downward compatible, i.e. it can be used in a 0 to 100 Kbit/s I
2
C bus
system.
Except from the bit rate selection (see Table 25) and the timing of
the SCL and SDA signals (see AC electrical characteristics in
section 11) the SIO circuit is the same as described in detail in the
80C51 Data Handbook IC20 for the 8xC552 microcontroller.
The I
2
C-bus is a simple bidirectional 2-wire bus for efficient inter-IC
data exchange. Features of the I
2
C-bus are:
• Only two bus lines are required: a serial clock line (SCL) and a
serial data line (SDA)
• Each device connected to the bus is software addressable by a
unique address
• Masters can operate as Master-transmitter or as Master-receiver
• It’s a true multi-master bus including collision detection and
arbitration to prevent data corruption if two or more masters
simultaneously initiate data transfer
• Serial clock synchronization allows devices with different bit rates
to communicate via the same serial bus
• ICs can be added to or removed from an I
2
C-bus system without
affecting any other circuit on the bus
• Fault diagnostics and debugging are simple; malfunctions can be
immediately traced
For more information on the I
2
C-bus specification (including
fast-mode) please refer to the Philips publication number 9398 393
40011 and/or the 80C51 Data Handbook IC20.
The on-chip I
2
C logic provides a serial interface that meets the
I
2
C-bus specification, supporting all I
2
C-bus modes of operation,
they are:
• Master transmitter
• Master receiver
• Slave transmitter
• Slave receiver
The SI01 logic performs a byte oriented data transport, clock
generation, address recognition and bus control arbitration are all
controlled by hardware. Via two pins the external I
2
C-bus is
interfaced to the SIO1 logic:
SCL serial clock I/O and SDA serial data I/O, (see Special Function
Register bit S1CON.6/ENS1 for enabling the SIO1 logic).
The SIO1 logic handles byte transfer autonomously. It keeps track of
the serial transfers, and a status register (S1STA) reflects the status
of SIO1 and the I
2
C-bus.
Via the following four Special Function Registers the CPU interfaces
to the I
2
C logic.
S1CON control register. Bit addressable by the CPU
S1STA status register whose contents may be used as a
vector to service routines.
S1DAT data shift register. The data byte is stable as long
as S1CON.3/SI=1.
S1ADR slave address register. It’s LSB enables/ disables
general call address recognition.
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P80C557E4EFB/01,55

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Buy P80C557E4EFB/01,55
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT ROMLESS 80QFP
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