M41T00AUD Operation
Doc ID 13480 Rev 5 13/42
4.2 Characteristics
4.3 READ mode
In this mode, the master reads the M41T00AUD slave after setting the slave address (see
Figure 8). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the
word (register) address An is written to the on-chip address pointer. Next the START
condition and slave address are repeated, followed by the READ mode control bit (R/W = 1).
At this point, the master transmitter becomes the master receiver. The data byte which was
addressed will be transmitted and the master receiver will send an acknowledge bit to the
slave transmitter. The address pointer is only incremented on reception of an acknowledge
bit. The device slave transmitter will now place the data byte at address An+1 on the bus.
The master receiver reads and acknowledges the new byte and the address pointer is
incremented to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
An alternate READ mode may also be implemented, whereby the master reads the
M41T00AUD slave without first writing to the (volatile) address pointer. The first address
that is read is the last one stored in the pointer (see Figure 10).
Table 3. AC characteristics
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 3.0 to 3.6 V (except where noted).
Min Typ Max Units
f
SCL
SCL clock frequency 0 400 kHz
t
LOW
Clock low period 1.3 µs
t
HIGH
Clock high period 600 ns
t
R
SDA and SCL rise time 300 ns
t
F
SDA and SCL fall time 300 ns
t
HD:STA
START condition hold time
(after this period the first clock pulse is generated)
600 ns
t
SU:STA
START condition setup time
(only relevant for a repeated start condition)
600 ns
t
SU:DAT
(2)
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
Data setup time 100 ns
t
HD:DAT
Data hold time 0 µs
t
SU:STO
STOP condition setup time 600 ns
t
BUF
Time the bus must be free before a new
transmission can start
1.3 µs
Operation M41T00AUD
14/42 Doc ID 13480 Rev 5
Figure 8. Slave address location
Figure 9. READ mode sequence
Figure 10. Alternate READ mode sequence
AI00602
R/W
SLAVE ADDRESS
START A
0100011
MSB
LSB
AI00899
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
S
START
R/W
SLAVE
ADDRESS
ACK
AI00895
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK
STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
SLAVE
ADDRESS
M41T00AUD Operation
Doc ID 13480 Rev 5 15/42
4.4 WRITE mode
In this mode the master transmitter transmits to the M41T00AUD slave receiver. Bus
protocol is shown in Figure 11. Following the START condition and slave address, a logic '0'
(R/W = 0) is placed on the bus and indicates to the addressed device that word address An
will follow and is to be written to the on-chip address pointer. The data word to be written to
the device is strobed in next and the internal address pointer is incremented to the next
location within the device on the reception of an acknowledge clock. The M41T00AUD slave
receiver will send an acknowledge clock to the master transmitter after it has received the
slave address and again after it has received the word address and each data byte (see
Figure 8).
Figure 11. WRITE mode sequence
4.5 Data retention mode
With valid V
CC
applied, the M41T00AUD can be accessed as described above with READ
or WRITE cycles. Should the supply voltage decay, the M41T00AUD will automatically
deselect, write protecting itself when V
CC
falls (see Figure 13).
AI00591
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
ACK
STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS

M41T00AUDD1F

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Real Time Clock SERIAL RTC W/AUDIO
Lifecycle:
New from this manufacturer.
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