M41T00AUD clock operation M41T00AUD
22/42 Doc ID 13480 Rev 5
5.4 Switchover thresholds
While the M41T00AUD includes a precision reference for the backup switchover threshold, it
is not a fixed value, but depends on the backup voltage, V
BACK
. The device will always
switchover at the lesser of the reference voltage (V
PFD
, approximately 2.8 V) and V
BACK
.
This ensures that it stays on V
CC
as long as possible before switching to the backup supply.
As shown in Figure 13, whenever V
BACK
is greater than V
PFD
, switchover occurs when V
CC
drops below V
PFD
.
Conversely, when V
BACK
is less than V
PFD
, switchover occurs when V
CC
drops below
V
BACK
. Ta ble 1 4 provides the values of these voltages.
Figure 13. Switchover thresholds
STAT E
On V
CC
On V
BACK
On V
CC
Switchover voltage
V
SO
= V
BACK
(< V
PFD
)
V
PFD
= 2.8V
V
CC
(= 3.3V)
Condition 2: V
BACK
< 2.8V (V
PFD
)
STAT E
On V
CC
On V
BACK
On V
CC
Switchover voltage
V
SO
= V
PFD
(= 2.8V)
V
BACK
(> V
PFD
)
V
CC
(= 3.3V)
Condition 1: V
BACK
> 2.8V (V
PFD
)
ai13326
M41T00AUD M41T00AUD clock operation
Doc ID 13480 Rev 5 23/42
5.5 Trickle charge circuit
The M41T00AUD includes a trickle charge circuit to be used with a backup capacitor. It is
illustrated in Figure 14. V
BACK
is a bi-directional pin. Its primary function is as the backup
supply input. (The input nature is not depicted in the figure.) The trickle charge output
function is a secondary capability, and reduces the need for external components.
To enable trickle charging, two switches must be closed. A diode is present to prevent
current from flowing backwards from V
BACK
to V
CC
. A current limiting resistor is also in the
path.
An additional switch allows the diode to be bypassed through a 20 k resistor. This should
charge the capacitor to a higher level thus extending backup life. This switch automatically
opens when the device switches to backup thus preventing capacitor discharge to V
CC
.
Furthermore, at switchover to backup, the other switches open as well. The application
must close them after power-up to re-enable the trickle charge function.
The use of two switches in the chain is to protect against accidental, unwanted charging as
might be the case when using battery backup. Additionally, one of the two switches requires
four bits to be changed from the default value before it will close. This prevents single bit
errors from closing the switch. The four bits, TCHE3:TCHE0, reside in register 09h at bits
D3 to D0.
The control bit for the second switch, TCH2, resides in register 08h at bit D5. With this bit in
a separate register, two bytes must be written before charging will occur, again protecting
against inadvertent charging due to errors.
The control bit for the bypass switch, TCFE, resides in register 09h at bit D6.
To enable trickle charging, the user must set TCHE3:TCHE0 to 5h, and TCH2 to 1. To
bypass the diode, TCFE must be set to 1. All three fields must be enabled after each power-
up.
Figure 14. Trickle charge circuit
TCHE
V
CC
TCHE/ = 5h
OPEN
TCHE = 5h
CLOSED
V
BACK
TCH2
TCH2 = 0
OPEN
TCH2 = 1
CLOSED
TCFE
TCFE = 0
OPEN
TCFE=1
CLOSED
ai13327
Clock calibration M41T00AUD
24/42 Doc ID 13480 Rev 5
6 Clock calibration
The M41T00AUD oscillator is designed for use with a 12.5 pF crystal load capacitance. With
a nominal ±20 ppm crystal, the M41T00AUD will be accurate to ±35 ppm. When the
calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25 °C.
The M41T00AUD design provides the following method for clock error correction.
6.1 Digital calibration (periodic counter correction)
This method employs the use of periodic counter correction by adjusting the number of
cycles of the internal 512 Hz signal counted in a second. By adding an extra cycle, for 513,
a long second is counted for slowing the clock. By reducing it to 511 cycles, a short second
is counted for speeding up the clock.
Not every second is affected. The calibration value (bits D4-D0 of register 07h) and its sign
bit (D5 of same register) control how often a short or long second is generated.
The basic nature of a 32 KHz crystal is to slow down at temperatures above and below
25 °C. Whether the temperature is above or below 25 °C, the device will tend to run slow.
Therefore, most corrections will need to speed the clock up. Hence, the M41T00AUD
calibration circuit uses a non-symmetric calibration scheme. Positive values, for speeding
the clock up, have more effect than negative values, for slowing it down. A positive value will
speed the clock up by approximately 4 ppm per step. A negative value will slow it by
approximately 2 ppm per step.
In the M41T00AUD's calibration circuit, positive correction is applied every 8
th
minute
whereas negative correction is applied every 16
th
minute. Because positive correction is
applied twice as often, it has twice the effect for a given calibration number, N. When the
calibration sign bit is positive, N seconds of every 8
th
minute will be shortened to 511 cycles
of the 512 Hz clock. When the calibration sign bit is negative, N seconds of every 16
th
minute will be lengthened to 513 cycles of the 512 Hz clock.
When N is positive, one minute will have N seconds which are 511 cycles and the remaining
seconds will be 512 cycles. The next seven minutes are nominal with all seconds 512
cycles each.
Example 1:
Sign is 1 and N is 2 (00010b)
The 8-minute interval will be:
2 * 511 + (60-2) * 512 + 7 * 60 * 512 = 245758 cycles long out of a possible
512 * 60 * 8 = 245760 cycles of the 512 Hz clock in an 8-minute span.
This gives a net correction of (245760-245758) / 245760 = -8.138 ppm
When N is negative, one minute will have N seconds which are 513 cycles and the
remaining seconds will be 512 cycles. The next 15 minutes are nominal with all seconds
512 cycles each.

M41T00AUDD1F

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Real Time Clock SERIAL RTC W/AUDIO
Lifecycle:
New from this manufacturer.
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