M41T00AUD Audio section operation
Doc ID 13480 Rev 5 31/42
The other parameter pertains to the gain step size, a relative measurement. It is shown in
Table 1 6 as 3±1 dB. For any gain setting in Tabl e 7 , the next higher (or lower) setting is
guaranteed to be between 2 and 4 dB higher (or lower). For example, even though no upper
and lower limits are shown for GAIN = Ch, it is tested to be at 3±1 dB of the case when
GAIN=Bh, one step below. If GAIN=Bh tests to -0.5 dB, then GAIN=Ch is tested to have an
end-to-end gain of 2.5±1 dB. If GAIN=Bh tests to +0.5 dB, then GAIN=Ch is tested to be
3.5±1 dB.
This applies to all steps except the lowest one (from GAIN=0 to GAIN=1) which is not tested.
In summary, for GAIN=1 to GAIN=Fh, all steps are tested to have a 1dB step size tolerance
of the listed 3 dB step size. The unity gain setting, Bh, will have an end-to-end gain of
0±1dB while the three levels for GAIN=4, 5 and Eh are tested to be within ±2 dB of the
typical gain values listed in Ta bl e 7 .
7.2 Wake-up time: T
WU
When the device powers on, the bypass capacitor C
BIAS
will not be charged immediately. As
C
BIAS
is directly linked to the bias of the amplifier, the amplifier will not work properly until
the capacitor is charged. The time to reach this voltage is called the wake-up time or T
WU
and is specified in the electrical characteristics, Tabl e 1 6 , for C
BIAS
= 1 µF.
Initial conditions M41T00AUD
32/42 Doc ID 13480 Rev 5
8 Initial conditions
The first time the M41T00AUD is powered up, some of its registers will automatically have
their bits set to pre-determined levels as depicted in the Tabl e 5 . Typically, these values are
set to benign levels to ensure predictable operation of the device.
ST, the stop bit, is a 0 at first power-up thus enabling the oscillator to run without need of
user intervention. On subsequent power-ups, it is not altered by the device and remains at
the last value programmed by the user. All other bits listed as unchanged (UC) in the table
behave similarly during power cycles.
The HT or halt bit is always set to 1 thus halting updates of the transfer buffer registers. The
user must write it to 0 to allow updates to resume.
The discrete output function available on the IRQ
/FT/OUT pin is set to 1. This is an open
drain output, and thus a 1 represents a high impedance condition.
FT or frequency test is always disabled on power-ups. The OF or oscillator fail bit will
always be 1 on the first power-up since the oscillator is always off prior to the first application
of V
CC
.
The trickle charger is always turned completely off after any power-up. The bits affecting it
are set to levels which keep all the trickle charge switches open. Both TCH2 and TCFE are
0 which opens their corresponding switches. TCHE3:TCHE0 are set to Ah, which is the
exact opposite of the value (5) required to close the corresponding switch.
On first power-up, the tone selects bits, 256/512 and TONE, are set to select the 512 hertz
tone, but have the function disabled (see Section 7). On subsequent power-ups, the
256/512 select bit remains unchanged, but TONE is always cleared. Furthermore, the
MUTE bit is always set to MUTE on all power-ups, disabling all audio.
The four-bit audio gain value is always set to the lowest setting (0) on initial power-up, but
remains unaffected by subsequent power cycles.
The 5-bit calibration register and its associated sign bit are set to 0 on initial power-up thus
resulting in no correction applied to the timekeeping operation. On subsequent power-ups,
the contents are not altered.
Table 8. Initial values
Condition ST HT OUT FT OF OFIE
TCHE
3:0
TCH2 TCFE
256
512
TONE MUTE GAIN
Cali-
bration
Initial
power-up
(1)
1. State of other control bits undefined
0
On
1101
0
Off
Ah
Off
0
Off
0
Off
1
512
0
Off
1
MUTE
0
–33 dB
0
Subsequent
power-up
(with
battery
backup)
UC
(2)
2. UC = unchanged
1 UC 0 UC UC
Ah
Off
0
Off
0
Off
UC
0
Off
1
MUTE
UC UC
M41T00AUD Maximum ratings
Doc ID 13480 Rev 5 33/42
9 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality
documents
Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the backup mode.
Table 9. Absolute maximum ratings
Symbol Parameter Value Unit
T
STG
Storage temperature (V
CC
off, oscillator off) –55 to 150 °C
T
J
Maximum junction temperature 150 °C
R
THJA
Thermal resistance junction to ambient 200 °C/W
V
CC
Supply voltage –0.3 to 4.5 V
T
SLD
(1)
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
Lead solder temperature for 10 seconds 260 °C
V
IO
Input or output voltages –0.3 to Vcc + 0.3 V
I
OA
Audio output current 300 mA
I
OD
Digital output current 20 mA
P
D
Power dissipation Internally limited

M41T00AUDD1F

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Real Time Clock SERIAL RTC W/AUDIO
Lifecycle:
New from this manufacturer.
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