M41T00AUDD1F Datasheet M41T00AUDD1F | P16-P18

M41T00AUD clock operation M41T00AUD

16/42 Doc ID 13480 Rev 5

5 M41T00AUD clock operation

5.1 Clock registers

The 10-byte register map (see Table 2 ) is used to both set the clock and to read the date

and time from the clock, in a binary coded decimal format.

Seconds, minutes, and hours are contained within the first three registers. Bits D6 to D0 or

range 0 to 59. Bit D7 is the ST or stop bit, described below, and is not affected by the

timekeeping operation, but users must avoid inadvertently altering it when writing the

seconds register.

Setting the ST bit to a 1 will cause the oscillator to stop. If the device is expected to spend a

significant amount of time on the shelf, the oscillator may be stopped to reduce current drain

on the backup battery. When reset to a 0 the oscillator restarts within one second.

In order to ensure oscillator start-up after the initial power-up, set the ST bit to a 1 then write

it to 0. This sequence enables the "kick start" circuit which aids the oscillator start-up by

temporarily increasing the oscillator current. This will guarantee oscillator start-up under

worst case conditions of voltage and temperature. This feature can be employed anytime

the oscillator is being started but should not occur on subsequent power-ups when the

oscillator is already running.

Bits D6 to D0 of register 01h (minutes register) contain the minutes count in BCD format

with values in the range 0 to 59. Bit D7 always reads 0. Writing it has no effect.

Bits D5 to D0 of register 02h (century/ hours register) contain the hours in BCD format with

values in the range 0 to 23. Bits D7 and D6 contain the century enable bit (CEB) and the

century bit (CB). CB provides a one-bit indicator for the century. The user can apply his

preferred convention for defining the meaning of this bit. For example, 0 can mean the

current century, and 1 the next, or the opposite meanings may be used.

When enabled, CB will toggle every 100 years. Setting CEB to a 1 enables CB to toggle at

the turn of the century, either from 0 to 1 or from 1 to 0, depending on its initial state, as

programmed by the user. When CEB is a 0, CB will not toggle.

Bits D2 through D0 of register 03h (day register) contain the day of the week in BCD format

with values in the range 0 to 7. Bits D3 and D7 will always read 0. Writes to them have no

effect. Bits D6, D5 and D4 will power up in an indeterminate state.

31. Bits D7 and D6 always read 0. Writes to them have no effect.

D5 always read 0. Writes to them have no effect.

the registers 00h to 06h, including the control bits therein, will result in updates to the

counters and resetting of the internal clock divider chain including the 256/512 Hz tone

generator. The updates do not occur immediately after the write(s), but occur upon

completion of the current write access. This is described in greater detail in the next section.

Registers 07h and 09h also contain clock control and status information. These registers

can be written at any time without affecting the timekeeping function.

M41T00AUD M41T00AUD clock operation

Doc ID 13480 Rev 5 17/42

calibration section. Bit D7 is the OUT bit and controls the discrete output pin IRQ

/FT/OUT as

described in Ta bl e 5 .

5.1.1 Halt bit operation

Bit D7 of register 09 h is the HT or halt bit. Whenever the device switches to backup power,

it sets the HT bit to 1 and stores the time of power-down in the transfer buffer registers. This

is known as power-down time stamp. During normal timekeeping, once per second, the

transfer buffer registers are updated with the current time. When HT is 1, that updating is

halted. The clock continues to keep time but the periodic updates do not occur.

Upon power-up, reads of the clock registers will return the time of power-down (assuming

adequate backup power was maintained while V

was off). After the user clears the HT bit

by writing it to 0, subsequent reads of the clock registers will return the current time.

At power-up, the user can read the time of power-down, and then clear the HT bit to allow

updates. The next read will return the current time. Knowing both the power-up time and the

power-down time allows the user to calculate the duration of power-off.

In addition to the HT bit getting set to 1 automatically at power-down, the user can also write

it to 1 to halt updating of the registers.

5.1.2 Oscillator fail detect operation

Bits D5 and D4 of register 09 h contain the oscillator fail flag (OF) and the oscillator fail

interrupt enable bit (OFIE). If the 32 KHz oscillator drops four or more pulses in a row, as

might occur during an extended outage while backed up on a capacitor, the OF bit will be set

to 1. This provides an indication to the user of the integrity of the timekeeping operation.

Whenever the OF bit is a 1, the system should consider the time to be possibly corrupted

due to operating at too low a voltage. The OF bit will always be 1 at the initial power-up of

the device. The OF bit is cleared by writing it to 0. At the initial power-up, users should wait

three seconds for the oscillator to stabilize before clearing the OF bit.

OFIE can be used to enable the device to assert its interrupt output whenever an oscillator

failure is detected. The oscillator fail interrupt will drive the IRQ

/FT/OUT pin as described in

Table 5. The interrupt is cleared by writing the OF bit to 0. Setting OFIE enables the

oscillator fail interrupt. Clearing it to 0 disables it, but the OF will continue to function

regardless of OFIE.

5.1.3 Trickle charger

Bits D6 and D3 to D0, of register 09h, control the trickle charge function. It is described in

detail in the trickle charge circuit section.

M41T00AUD clock operation M41T00AUD

18/42 Doc ID 13480 Rev 5

5.2 Reading and writing the clock registers

The counters used to implement the timing chain in the real-time clock are not directly

accessed by the serial interface. Instead, as depicted in Figure 12, reads and writes are

buffered through a set of transfer registers. This ensures coherency of the timekeeping

function.

During writes of the timekeeping registers (00h to 06h), the write data is stored in the buffer

transfer registers until all the data is written, then the register contents are simultaneously

transferred to the counters thus updating them. The update is triggered either by a STOP

condition or by a write to one of the non RTC registers, 07h to 09h. If any of the buffer

transfer registers are not written, then the corresponding counters are not updated. Instead,

those counters will retain their previous contents when the update occurs.

Similar to the writes, reads access the buffer transfer registers. The device periodically

updates the registers with the counter contents. But during reads, the updates are

suspended. Timekeeping continues, but the registers are frozen until after a STOP

condition or a non RTC register (07h to 09h) is read. Suspending the updates ensures that

a clock roll-over does not occur during a user read cycle.

The seven clock registers may be read one byte at a time, or in a sequential block. The

calibration, audio and Control2 registers, location 07 h to 09 h, may be accessed

independently.

Provision has been made to ensure that a clock update does not occur while any of the

seven clock addresses are being read. During a clock register read (addresses 00h to 06h),

updates of the clock transfer buffer registers are halted. The clock counters continue to keep

time, but the contents of the transfer buffer registers is frozen at the time that the read

access began.

This prevents a transition of data during the READ. For example, without the halt function, if

the time incremented past midnight in the middle of an access sequence, the user might

begin reading at 11:59:59pm and finish at 12:00:00am. The data read might appear as

12:59:59 because the seconds and minutes were read before midnight while the hours were

read after. The device prevents this by halting the updates of the registers until after the read

access has occurred.

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M41T00AUDD1F

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STMicroelectronics

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Real Time Clock SERIAL RTC W/AUDIO

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