P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 28 September 2007 12 of 66
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Table 5. P89LPC913 pin description
Symbol Pin Type Description
P0.2,
P0.4 to P0.6
I/O Port 0: Port 0 is a 4-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 0 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to
Section
8.12.1 “Port configurations” and Table 13 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.2/CIN2A/
KBI2
13 I/O P0.2 — Port 0 bit 2.
I CIN2A — Comparator 2 positive input A.
I KBI2 — Keyboard input 2.
P0.4/CIN1A/
KBI4
12 I/O P0.4 — Port 0 bit 4.
I CIN1A — Comparator 1 positive input A.
I KBI4 — Keyboard input 4.
P0.5/CMPREF/
KBI5
11 I/O P0.5 — Port 0 bit 5.
I CMPREF — Comparator reference (negative) input.
I KBI5 — Keyboard input 5.
P0.6/CMP1/
KBI6
5 I/O P0.6 — Port 0 bit 6.
O CMP1 — Comparator 1 output.
I KBI6 — Keyboard input 6.
P1.0, P1.1,
P1.5
I/O
(P1.0,
P1.1);
I (P1.5)
Port 1: Port 1 is a 3-bit I/O port with a user-configurable output type, except for P1.5
noted below. During reset Port 1 latches are configured in the input only mode with
the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs
and outputs depends upon the port configuration selected. Each of the configurable
port pins are programmed independently. Refer to
Section 8.12.1 “Port
configurations” and Table 13 “Static characteristics” for details. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD 9 I/O P1.0 — Port 1 bit 0.
O TXD — Transmitter output for the serial port.
P1.1/RXD 6 I/O P1.1 — Port 1 bit 1.
I RXD — Receiver input for the serial port.
P1.5/
RST 3 I P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing
I/O ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force ISP mode.
When using an oscillator frequency above 12 MHz, the reset input function of
P1.5 must be enabled. An external circuit is required to hold the device in
reset at power-up until V
DD
has reached its specified level. When system
power is removed V
DD
will fall below the minimum specified operating
voltage. When using an oscillator frequency above 12 MHz, in some
applications, an external brownout detect circuit may be required to hold the
device in reset when V
DD
falls below the minimum specified operating
voltage.
