P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 28 September 2007 57 of 66
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
[1] Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to
operate down to 0 Hz.
[2] When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to
hold the device in reset at power-up until V
DD
has reached its specified level. When system power is removed V
DD
will fall below the
minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout
detect circuit may be required to hold the device in reset when V
DD
falls below the minimum specified operating voltage.
11.1 Waveforms
t
SPIF
SPI fall time see Figure 26,
27, 28, 29
SPI outputs (SPICLK, MOSI,
MISO)
- 100 - 100 ns
SPI inputs (SPICLK, MOSI,
MISO,
SS)
- 2000 - 2000 ns
Table 15. Dynamic characteristics (P89LPC912, P89LPC913)
…continued
V
DD
= 3.0 V to 3.6 V, unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C for industrial,
−
40
°
C to +125
°
C for extended, unless otherwise specified.
[1]
Symbol Parameter Conditions Variable clock f
osc
= 18 MHz Unit
Min Max Min Max
Fig 24. Shift register mode timing
01234567
valid valid valid valid valid valid valid valid
T
XLXL
002aaa906
set TI
set RI
t
XHQX
t
QVXH
t
XHDV
t
XHDX
clock
output data
write to SBUF
input data
clear RI
Fig 25. External clock timing
t
CHCL
t
CLCX
t
CHCX
T
cy(clk)
t
CLCH
002aaa907
0.2V
DD
+ 0.9 V
0.2V
DD
− 0.1 V
V
DD
− 0.5 V
0.45 V
