P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 28 September 2007 40 of 66
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
8.18.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),
8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 8.18.5
“Baud rate generator and selection”).
8.18.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data
bits (LSB first), a programmable 9
th
data bit, and a stop bit (logic 1). When data is
transmitted, the 9
th
data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.
Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is
received, the 9
th
data bit goes into RB8 in Special Function Register SCON, while the stop
bit is not saved. The baud rate is programmable to either
1
⁄
16
or
1
⁄
32
of the CCLK
frequency, as determined by the SMOD1 bit in PCON.
8.18.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9
th
data bit, and a stop bit (logic 1). In fact, Mode 3 is
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in
section Section 8.18.5 “Baud rate generator and selection”).
8.18.5 Baud rate generator and selection
The P89LPC913 and P89LPC914 devices have an independent Baud Rate Generator.
The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0
SFRs which together form a 16-bit baud rate divisor value that works in a similar manner
as Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing
functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 15). Note
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses CCLK.
8.18.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is logic 1, framing errors can be made available in SCON.7, respectively. If SMOD0 is
logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are set up
when SMOD0 is logic 0.
Fig 15. Baud rate sources for UART (Modes 1, 3)
baud rate modes 1 and 3
SBRGS = 1
SBRGS = 0
SMOD1 = 0
SMOD1 = 1
timer 1 overflow
(PCLK-based)
baud rate generator
(CCLK-based)
002aaa419
÷2
