P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 28 September 2007 58 of 66
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Fig 26. SPI master timing (CPHA = 0)
T
SPICYC
t
SPICLKH
t
SPICLKH
t
SPICLKL
t
SPICLKL
master LSB/MSB outmaster MSB/LSB out
t
SPIDH
t
SPIDSU
t
SPIF
t
SPIOH
t
SPIDV
t
SPIR
t
SPIDV
t
SPIF
t
SPIR
t
SPIF
t
SPIR
SS
SPICLK
(CPOL = 0)
(output)
002aaa908
SPICLK
(CPOL = 1)
(output)
MISO
(input)
MOSI
(output)
LSB/MSB in
MSB/LSB in
Fig 27. SPI master timing (CPHA = 1)
T
SPICYC
t
SPICLKL
t
SPICLKL
t
SPICLKH
t
SPICLKH
master LSB/MSB outmaster MSB/LSB out
t
SPIDH
t
SPIDSU
t
SPIF
t
SPIOH
t
SPIDV
t
SPIDV
t
SPIR
t
SPIDV
t
SPIF
t
SPIF
t
SPIR
t
SPIR
SS
SPICLK
(CPOL = 0)
(output)
002aaa909
SPICLK
(CPOL = 1)
(output)
MISO
(input)
MOSI
(output)
LSB/MSB in
MSB/LSB in
P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 28 September 2007 59 of 66
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Fig 28. SPI slave timing (CPHA = 0)
T
SPICYC
t
SPICLKH
t
SPICLKH
t
SPICLKL
t
SPICLKL
t
SPILEAD
t
SPILAG
t
SPIDSU
t
SPIDH
t
SPIDH
t
SPIDSU
t
SPIDSU
t
SPIR
t
SPIA
t
SPIOH
t
SPIDIS
t
SPIR
slave MSB/LSB out
MSB/LSB in LSB/MSB in
slave LSB/MSB out
t
SPIDV
t
SPIOH
t
SPIOH
t
SPIDV
t
SPIR
t
SPIR
t
SPIF
t
SPIF
SS
SPICLK
(CPOL = 0)
(input)
002aaa910
SPICLK
(CPOL = 1)
(input)
MISO
(output)
MOSI
(input)
not defined
Fig 29. SPI slave timing (CPHA = 1)
002aaa911
T
SPICYC
t
SPICLKH
t
SPICLKH
t
SPICLKL
t
SPILEAD
t
SPICLKL
t
SPILAG
t
SPIDSU
t
SPIDSU
t
SPIDSU
t
SPIDH
t
SPIDH
t
SPIR
t
SPIR
t
SPIR
t
SPIA
t
SPIOH
t
SPIOH
t
SPIOH
t
SPIDIS
slave MSB/LSB out
not defined
MSB/LSB in LSB/MSB in
slave LSB/MSB out
t
SPIDV
t
SPIDV
t
SPIDV
t
SPIR
t
SPIF
t
SPIF
SS
SPICLK
(CPOL = 0)
(input)
SPICLK
(CPOL = 1)
(input)
MISO
(output)
MOSI
(input)
P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 28 September 2007 60 of 66
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
12. Other characteristics
12.1 Comparator electrical characteristics
[1] This parameter is characterized, but not tested in production.
Table 16. Comparator electrical characteristics
V
DD
= 2.4 V to 3.6 V, unless otherwise specified.
T
amb
=
40
°
C to +85
°
C for industrial,
40
°
C to +125
°
C for extended, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V
IO
input offset voltage - - ±10 mV
V
IC
common-mode input voltage 0 - V
DD
0.3 V
CMRR common-mode rejection ratio
[1]
--50 dB
t
res(tot)
total response time - 250 500 ns
t
(CE-OV)
chip enable to output valid time - - 10 µs
I
LI
input leakage current 0 V < V
I
<V
DD
--±1 µA

P89LPC914FDH,129

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 1KB FLASH 14TSSOP
Lifecycle:
New from this manufacturer.
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