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P89LPC914FDH,129

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66
P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 28 September 2007 13 of 66
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
P2.2, P2.3,
P2.5
I/O Port 2: Port 2 is a 3-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to
Section
8.12.1 “Port configurations” and Table 13 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below:
P2.2/MOSI 1 I/O P2.2 — Port 2 bit 2.
I/O MOSI — SPI master out slave in. When configured as master, this pin is output,
when configured as slave, this pin is input.
P2.3/MISO 14 I/O P2.3 — Port 2 bit 3.
I/O MISO — SPI master in slave out. When configured as master, this pin is input,
when configured as slave, this pin is output.
P2.5/SPICLK 2 I/O P2.5 — Port 2 bit 5.
I/O SPICLK — SPI clock. When configured as master, this pin is output, when
configured as slave, this pin is input.
P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 3 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to
Section
8.12.1 “Port configurations” and Table 13 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below:
P3.0/XTAL2/
CLKOUT
8 I/O P3.0 — Port 3 bit 0.
O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the flash configuration).
O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6).
It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source
for the Real-Time clock/system timer.
P3.1/XTAL1 7 I/O P3.1 — Port 3 bit 1.
I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the flash configuration). It can be a port pin if internal RC oscillator or
watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not
used to generate the clock for the Real-Time clock/system timer.
V
SS
4IGround: 0 V reference.
V
DD
10 I Power Supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
Table 5. P89LPC913 pin description
…continued
Symbol Pin Type Description
P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 28 September 2007 14 of 66
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Table 6. P89LPC914 pin description
Symbol Pin Type Description
P0.2,
P0.4 to P0.6
I/O Port 0: Port 0 is a 4-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 0 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to
Section
8.12.1 “Port configurations” and Table 13 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.2/CIN2A/
KBI2
13 I/O P0.2 — Port 0 bit 2.
I CIN2A — Comparator 2 positive input A.
I KBI2 — Keyboard input 2.
P0.4/CIN1A/
KBI4
12 I/O P0.4 — Port 0 bit 4.
I CIN1A — Comparator 1 positive input A.
I KBI4 — Keyboard input 4.
P0.5/CMPREF
/ KBI5
11 I/O P0.5 — Port 0 bit 5.
I CMPREF — Comparator reference (negative) input.
I KBI5 — Keyboard input 5.
P0.6/CMP1/
KBI6
5 I/O P0.6 — Port 0 bit 6.
O CMP1 — Comparator 1 output.
I KBI6 — Keyboard input 6.
P1.0 to P1.2,
P1.5
I/O
(P1.0 to
P1.2);
I (P1.5)
Port 1: Port 1 is a 4-bit I/O port with a user-configurable output type, except for
three pins noted below. During reset Port 1 latches are configured in the input only
mode with the internal pull-up disabled. The operation of the configurable Port 1
pins as inputs and outputs depends upon the port configuration selected. Each of
the configurable port pins are programmed independently. Refer to
Section 8.12.1
“Port configurations” and Table 13 “Static characteristics” for details. P1.2 is an
open drain when used as an output. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD 9 I/O P1.0 — Port 1 bit 0.
O TXD — Transmitter output for the serial port.
P1.1/RXD 6 I/O P1.1 — Port 1 bit 1.
I RXD — Receiver input for the serial port.
P1.2/T0 7 I/O P1.2 — Port 1 bit 2. (Open drain when used as an output.)
I/O T0 — Timer/counter 0 external count input or overflow output. (Open drain when
used as outputs.)
P1.5/
RST 3 I P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during Power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing
I/O ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force ISP mode.
P89LPC912_913_914_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 28 September 2007 15 of 66
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
P2.2 to P2.5 I/O Port 2: Port 2 is a 4-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up
disabled. The operation of Port 2 pins as inputs and outputs depends upon the port
configuration selected. Each port pin is configured independently. Refer to
Section
8.12.1 “Port configurations” and Table 13 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below:
P2.2/MOSI 1 I/O P2.2 — Port 2 bit 2.
I/O MOSI — SPI master out slave in. When configured as master, this pin is output,
when configured as slave, this pin is input.
P2.3/MISO 14 I/O P2.3 — Port 2 bit 3.
I/O MISO — SPI master in slave out. When configured as master, this pin is input,
when configured as slave, this pin is output.
P2.4/
SS 8 I/O P2.4 — Port 2 bit 4.
I
SS — SPI Slave select.
P2.5/SPICLK 2 I/O P2.5 — Port 2 bit 5.
I/O SPICLK — SPI clock. When configured as master, this pin is output, when
configured as slave, this pin is input.
V
SS
4IGround: 0 V reference.
V
DD
10 I Power Supply: This is the power supply voltage for normal operation as well as
Idle and Power-down modes.
Table 6. P89LPC914 pin description
…continued
Symbol Pin Type Description
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66

P89LPC914FDH,129

Mfr. #:
Buy P89LPC914FDH,129
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 1KB FLASH 14TSSOP
Lifecycle:
New from this manufacturer.
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