12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
™™
™™
™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
AC ELECTRICAL CHARACTERISTICS
(1)
— SYNCHRONOUS TIMING
(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
Commercial Com’l & Ind’l Commercial
IDT72T3645L4-4 IDT72T3645L5 IDT72T3645L6-7
IDT72T3655L4-4 IDT72T3655L5 IDT72T3655L6-7
IDT72T3665L4-4 IDT72T3665L5 IDT72T3665L6-7
IDT72T3675L4-4 IDT72T3675L5 IDT72T3675L6-7
IDT72T3685L4-4 IDT72T3685L5 IDT72T3685L6-7
IDT72T3695L4-4 IDT72T3695L5 IDT72T3695L6-7
IDT72T36105L4-4 IDT72T36105L5 IDT72T36105L6-7 IDT72T36105L10
IDT72T36115L4-4 IDT72T36115L5 IDT72T36115L6-7 IDT72T36115L10
IDT72T36125L4-4 IDT72T36125L5 IDT72T36125L6-7 IDT72T36125L10
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
fC Clock Cycle Frequency (Synchronous) — 225 — 200 — 150 100 MHz
tA Data Access Time 0.6 3.4 0.6 3.6 0.6 3.8 0.6 4.5 ns
tCLK Clock Cycle Time 4.44 — 5 — 6.7 — 10 — ns
tCLKH Clock High Time 2.0 — 2.3 — 2.8 — 4.5 — ns
tCLKL Clock Low Time 2.0 — 2.3 — 2.8 — 4.5 — ns
tDS Data Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tDH Data Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tENS Enable Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tENH Enable Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tLDS Load Setup Time 1.2 — 1.5 — 2.0 — 3.0 — ns
tLDH Load Hold Time 0.5 — 0.5 — 0.5 — 0.5 — ns
tWCSS WCS setup time 1.2 — 1.5 — 2.0 — 3.0 — ns
tWCSH WCS hold time 0.5 — 0.5 — 0.5 — 0.5 — ns
fS Clock Cycle Frequency (SCLK) — 10 — 10 — 10 — 10 MHz
tSCLK Serial Clock Cycle 100 — 100 — 100 — 100 — ns
tSCKH Serial Clock High 45 — 45 — 45 — 45 — ns
tSCKL Serial Clock Low 45 — 45 — 45 — 45 — ns
tSDS Serial Data In Setup 15 — 15 — 15 — 15 — ns
tSDH Serial Data In Hold 5 — 5 — 5 — 5 — ns
tSENS Serial Enable Setup 5 — 5 — 5 — 5 — ns
tSENH Serial Enable Hold 5 — 5 — 5 — 5 — ns
tRS Reset Pulse Width
(2)
30 — 30 — 30 — 30 — ns
tRSS Reset Setup Time 15 — 15 — 15 — 15 — ns
tHRSS HSTL Reset Setup Time 4 — 4 — 4 — 4 — µs
tRSR Reset Recovery Time 10 — 10 — 10 — 10 — ns
tRSF Reset to Flag and Output Time — 10 — 12 — 15 — 15 ns
tWFF Write Clock to FF or IR — 3.4 — 3.6 — 3.8 — 4.5 ns
tREF Read Clock to EF or OR — 3.4 — 3.6 — 3.8 — 4.5 ns
tPAFS Write Clock to Synchronous Programmable Almost-Full Flag — 3.4 — 3.6 — 3.8 — 4.5 ns
tPAES Read Clock to Synchronous Programmable Almost-Empty Flag — 3.4 — 3.6 — 3.8 — 4.5 ns
tERCLK RCLK to Echo RCLK output — 3.8 — 4 — 4.3 — 5 ns
tCLKEN RCLK to Echo REN output — 3.4 — 3.6 — 3.8 — 4.5 ns
tRCSLZ RCLK to Active from High-Z
(3)
— 3.4 — 3.6 — 3.8 — 4.5 ns
tRCSHZ RCLK to High-Z
(3)
— 3.4 — 3.6 — 3.8 — 4.5 ns
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR 3.5— 4 —5 —7 —ns
t
SKEW2 Skew time between RCLK and WCLK for PAE and PAF 4—5—6 —8—ns
