49
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the
IDT72T3685, 32,768 for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.
2. In FWFT mode: D = maximum FIFO depth. D = 1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the
IDT72T3685, 32,769 for the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.
3. RCS = LOW.
Figure 27. Half-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
t
ENS
t
ENH
WEN
HF
t
ENS
t
HF
RCLK
t
HF
REN
5907 drw32
t
CLKL
t
CLKH
D/2 words in FIFO
(1)
,
[
+ 1
]
words in FIFO
(2)
D-1
2
D/2 + 1 words in FIFO
(1)
,
[
+ 2
]
words in FIFO
(2)
D/2 words in FIFO
(1)
,
[
+ 1
]
words in FIFO
(2)
D-1
2
D-1
2
50
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
Figure 28. Echo Read Clock & Read Enable Operation (IDT Standard Mode Only)
t
ENS
t
ENH
t
ENS
RCS
RCLK
REN
Qn
t
ERCLK
t
ENS
5907 drw33
ERCLK
t
ENH
EREN
t
CLKEN
t
CLKEN
t
CLKEN
t
CLKEN
t
REF
EF
W
D-4
t
A
t
OLZ
t
OHZ
t
A
t
OLZ
t
A
t
A
Last Word, W
D
W
D-3
W
D-3
W
D-2
W
D-1
t
CLKEN
t
CLKEN
NOTES:
1. The EREN output is an “ANDed” function of RCS and REN and will follow these inputs provided that the FIFO is not empty. If the FIFO is empty, EREN will go HIGH, thus preventing any reads.
2. The EREN output is synchronous to RCLK.
51
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
Figure 29. Echo RCLK and Echo
RENREN
RENREN
REN
Operation (FWFT Mode Only)
NOTE:
1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS and OE are both active, LOW, that is the bus is not in High-
Impedance state.
2. OE is LOW.
Cycle:
a&b. At this point the FIFO is empty, OR is HIGH.
RCS and REN are both disabled, the output bus is High-Impedance.
c. Word Wn+1 falls through to the output register, OR goes active, LOW.
RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.
d. EREN goes HIGH, no new word has been placed on the output register on this cycle.
e. No Operation.
f. RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
g. REN goes active LOW, this reads out the second word, Wn+2.
EREN goes active LOW to indicate a new word has been placed into the output register.
h. Word Wn+3 is read out, EREN remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
i. This is the next enabled read after the last word, Wn+3 has been read out. OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.
Qn
O/P
Reg.
t
A
t
REF
OR
5907 drw34
t
RCSLZ
REN
t
ENS
t
ENH
RCS
t
ENS
RCLK
a
b
c
d
e
f
g
h
i
W
n+1
WCLK
WEN
D0 - Dn
t
SKEW1
t
ENS
t
DS
t
ENH
W
n+2
W
n+3
ERCLK
EREN
t
CLKEN
t
CLKEN
t
CLKEN
t
CLKEN
W
n+1
W
n+2
W
n+3
t
A
t
REF
W
n+1
W
n+2
W
n+3
t
A
W
n
Last Word
t
A
t
A
t
DH
t
DH
t
DH
t
DS
t
DS
1
2
t
ERCLK
HIGH-Z

72T3695L5BB

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 2.5V 32K X 36 FIFO
Lifecycle:
New from this manufacturer.
Delivery:
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