40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
™™
™™
™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
Figure 14. Write Timing (First Word Fall Through Mode)
NOTES:
1. t
SKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than t
SKEW1, then OR assertion may be delayed one extra RCLK cycle.
2. t
SKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than t
SKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. D = 1,025 for IDT72T3645, 2,049 for IDT72T3655, 4,097 for IDT72T3665, 8,193 for IDT72T3675, 16,385 for IDT72T3685, 32,769 for the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for
the IDT72T36125.
6. First data word latency = t
SKEW1 + 2*TRCLK + tREF.
W
1
W
2
W
4
W
[n +2]
W
[D-m-1]
W
[D-m-2]
W
[D-1]
W
D
W
[n+3]
W
[n+4]
W
[D-m]
W
[D-m+1]
WCLK
WEN
D0 - Dn
RCLK
t
DH
t
DS
t
SKEW1
(1)
REN
Q0 - Qn
PAF
HF
PAE
IR
t
DS
t
DS
t
DS
t
SKEW2
t
A
t
REF
OR
t
PAES
t
HF
t
PAFS
t
WFF
W
[D-m+2]
W
1
t
ENH
5907 drw 19
PREVIOUS DATA IN OUTPUT REGISTER
(2)
W
3
1
2
3
1
D-1
][
W
D-1
][
W
D-1
][
W
1
2
t
ENS
RCS
t
RCSLZ
t
ENS
