46
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. X = 10 for the IDT72T3645, X = 11 for the IDT72T3655, X = 12 for the IDT72T3665, X = 13 for the IDT72T3675, X = 14 for the IDT72T3685, X = 15 for the IDT72T3695, X = 16
for the IDT72T36105, X = 17 for the IDT72T36115 and X = 18 for the IDT72T36125.
SCLK
SEN
SI
5907 drw25
LD
EMPTY OFFSET
FULL OFFSET
BIT X
(1)
t
SENS
t
LDS
t
SDS
t
SENH
t
LDS
BIT X
(1)
BIT 1
t
ENH
t
LDH
t
SDH
t
SCLK
t
SCKH
t
SCKL
BIT 1
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
3. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
WCLK
LD
WEN
D
0
- D
n
5907 drw26
PAE
OFFSET
PAF
OFFSET
t
DH
t
LDH
t
ENH
t
DH
t
ENH
t
LDH
t
ENS
t
LDS
t
DS
t
CLK
t
CLKH
t
CLKL
RCLK
LD
REN
Q
0
- Q
n
DATA IN OUTPUT REGISTER PAE OFFSET VALUE PAF OFFSET VALUE
5907 drw27
tLDH
tENH
tCLK
tCLKL
tCLKH
tA
tLDS
tLDH
tLDS
tLDH
tLDS
tENS
tENH
tENS
tENH
tENS
tA
PAE OFFSET
tA
47
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665 and 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768
for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.
In FWFT mode: D = 1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695,
65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.
3.
t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
PAFS
). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAF
RCLK
REN
5907 drw28
1
2
12
D-(m+1) words
in FIFO
(2)
D - m words in FIFO
(2)
D - (m +1) words in FIFO
(2)
t
ENH
t
ENS
t
PAFS
t
ENS
t
ENH
t
CLKL
t
CLKL
t
SKEW2
(3)
t
PAFS
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4.
tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7. RCS = LOW.
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAE
RCLK
12 12
REN
5907 drw29
n + 1 words in FIFO
(2)
,
n + 2 words in FIFO
(3)
t
ENS
t
SKEW2
(4)
t
ENH
t
PAES
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
t
PAES
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
t
ENS
t
ENH
t
CLKH
t
CLKL
48
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode:
D=1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the
IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.
In FWFT Mode: D=1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695,
65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
5. RCS = LOW.
Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAF
D - (m + 1) words
in FIFO
RCLK
t
PAFA
REN
5907 drw30
D - m words
in FIFO
D - (m + 1) words in FIFO
t
ENS
t
PAFA
t
ENH
t
ENS
t
CLKL
t
CLKH
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
6. RCS = LOW.
Figure 26. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAE
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
RCLK
REN
5907 drw31
tPAEA
n + 1 words in FIFO
(2)
,
n + 2 words in FIFO
(3)
tPAEA
tENS
tENS tENH
tCLKLtCLKH
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)

72T3695L5BB

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 2.5V 32K X 36 FIFO
Lifecycle:
New from this manufacturer.
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