21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
™™
™™
™ 36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, SEN, SCLK and SI input pins. Programming PAE and PAF proceeds
as follows: when LD and SEN are set LOW, data on the SI input are written, one
bit for each SCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. A total of 20 bits for the IDT72T3645, 22 bits for the
IDT72T3655, 24 bits for the IDT72T3665, 26 bits for the IDT72T3675, 28 bits
for the IDT72T3685, 30 bits for the IDT72T3695, 32 bits for the IDT72T36105,
34 bits for the IDT72T36115 and 36 bits for the IDT72T36125. See Figure 20,
Serial Loading of Programmable Flag Registers, for the timing diagram for this
mode.
Using the serial method, individual registers cannot be programmed
selectively. PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does not
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing LD and SEN HIGH, data can be written to FIFO memory via
Dn by toggling WEN. When WEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruption of serial programming is desired, it is sufficient either to set LD LOW
and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising SCLK edge that achieves the above criteria;
PAF will be valid after three more rising WCLK edges plus tPAF, PAE will be valid
after the next three rising RCLK edges plus tPAE.
It is only possible to read the flag offset values via the parallel output port Qn.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, WCLK , WEN and Dn input pins. Programming PAE and PAF
proceeds as follows: LD and WEN must be set LOW. When programming the
Offset Registers of the TeraSync FIFO’s the number of programming cycles will
be based on the bus width, the following rules apply:
When a 36 bit input bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125, 2 enabled write cycles are required to
program the offset registers, (1 per offset). Data on the inputs Dn are written into
the Empty Offset Register on the first LOW-to-HIGH transition of WCLK. Upon
the second LOW-to-HIGH transition of WCLK, data are written into the Full Offset
Register. The third transition of WCLK writes, once again, to the Empty Offset
Register.
When an 18 bit input bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105, 2 enabled write cycles are required to program the offset registers,
(1 per offset). Data on the inputs Dn are written into the Empty Offset Register
on the first LOW-to-HIGH transition of WCLK. Upon the second LOW-to-HIGH
transition of WCLK, data are written into the Full Offset Register. The third
transition of WCLK writes, once again, to the Empty Offset Register.
For the IDT72T36115/72T36125, 4 enabled write cycles are required to
load the offset registers, (2 per offset). Data on the inputs Dn are written into the
Empty Offset Register LSB on the first LOW-to-HIGH transition of WCLK. Upon
the 2
nd
LOW-to-HIGH transition of WCLK data on the inputs Dn are written into
the Empty Offset Register MSB. Upon the 3
rd
LOW-to-HIGH transition of WCLK
data on the inputs Dn are written into the Full Offset Register LSB. Upon the 4
th
LOW-to-HIGH transition of WCLK data on the inputs Dn are written into the Full
Offset Register MSB. The 5
th
LOW-to-HIGH transition of WCLK data on the inputs
Dn are once again written into the Empty Offset Register LSB.
When a 9 bit input bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105, 4 enabled write cycles are required to load the offset registers, (2
per offset). Data on the inputs Dn are written into the Empty Offset Register LSB
on the first LOW-to-HIGH transition of WCLK. Upon the 2
nd
LOW-to-HIGH
transition of WCLK data on the inputs Dn are written into the Empty Offset Register
MSB. Upon the 3
rd
LOW-to-HIGH transition of WCLK data on the inputs Dn are
written into the Full Offset Register LSB. Upon the 4
th
LOW-to-HIGH transition
of WCLK data on the inputs Dn are written into the Full Offset Register MSB. The
5
th
LOW-to-HIGH transition of WCLK data on the inputs Dn are once again written
into the Empty Offset Register LSB.
For the IDT72T36115/72T36125, 6 enabled write cycles are required to
load the offset registers, (3 per offset). Data on the inputs Dn are written into the
Empty Offset Register LSB on the first LOW-to-HIGH transition of WCLK. Upon
the 3
rd
LOW-to-HIGH transition of WCLK data on the inputs Dn are written into
the Empty Offset Register MSB. Upon the 4
th
LOW-to-HIGH transition of WCLK
data on the inputs Dn are written into the Full Offset Register LSB. Upon the 6
th
LOW-to-HIGH transition of WCLK data on the inputs Dn are written into the Full
Offset Register MSB. The 7
th
LOW-to-HIGH transition of WCLK data on the inputs
Dn are once again written into the Empty Offset Register LSB. See Figure 3,
Programmable Flag Offset Programming Sequence. See Figure 21, Parallel
Loading of Programmable Flag Registers, for the timing diagram for this mode.
The act of writing offsets in parallel employs a dedicated write offset register
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A Master Reset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers does
not have to occur at one time. One, two or more offset registers can be written
and then by bringing LD HIGH, write operations can be redirected to the FIFO
memory. When LD is set LOW again, and WEN is LOW, the next offset register
in sequence is written to. As an alternative to holding WEN LOW and toggling
LD, parallel programming can also be interrupted by setting LD LOW and
toggling WEN.
Note that the status of a programmable flag (PAE or PAF) output is invalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria; PAF will be valid after
two more rising WCLK edges plus tPAF, PAE will be valid after the next two rising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-Qn
pins when LD is set LOW and REN is set LOW. It is important to note that
consecutive reads of the offset registers is not permitted. The read operation must
be disabled for a minimum of one RCLK cycle in between offset register
accesses. When reading the Offset Registers of the TeraSync FIFO’s the
number of reading cycles will be based on the bus width, the following rules
apply:
