SC28C94A1A,512 Datasheet SC28C94A1A,512, SC28C94A1A,518, SC28C94A1N,112 | P10-P12

Philips Semiconductors Product data sheet

SC28C94Quad universal asynchronous receiver/transmitter (QUART)

2006 Aug 09

WAKE-UP MODE (MULTI-DROP OR 9-BIT)

In addition to the normal transmitter and receiver operation described

above, the QUART incorporates a special mode which provides

automatic “wake up” of a receiver through address frame (or character)

recognition for multi-processor or multi-station communications. This

mode is selected by programming MR1[4:3] to ‘11’.

In this mode of operation a ‘master’ station transmits an address

character to the several ‘slave’ stations on the line. The address

character is identified by setting its parity bit to 1. The slave stations

will usually have their receivers partially enabled as a result of

setting MR1[4:3] to 11. When the receiver sees a one in the parity

position, it considers it an address bit and loads that character to the

RxFIFO and set the RxRDY bit in the status register. The user

would usually set the receiver interrupt to occur on RxRDY as well.

(All characters whose parity bits are set to 0 will be ignored). The

local processor at the slave station will read the ‘address’ character

just received. The local processor will test for an address match for

this station and if match occurs it will enable the local receiver and

receive the following data characters. The master will normally

follow an address character(s) with data characters. Since the data

characters transmitted by the master will have their parity bits set to

zero, stations other than the addressed one(s) will ignore the data.

NOTE: The time between address and data fields must be

enough for the local processor to test the address character

and enable the receiver. At bit times approaching 10µs this may

begin to be a point of concern.

The parity (Address/Data) bit should not be changed until the last stop

bit of an address has been sent. Similarly the A/D bit should not be

changed to address until the last stop bit has been sent. Either of

these conditions will be indicated by an active TxEMT bit in the SR.

The parity bit is not part of the TxFIFO. It is in the transmitter state

machine. However, it could be controlled in the FIFO if 5, 6 or 7 bit

data was transmitted by using a 6, 7 or 8 bit character. The most

significant bit would then be in the ‘parity’ position and represent the

A/D bit. The design of the UART is based, however, on the A/D bit

being controlled from the MR register.

Parity should be changed immediately before the data bytes

will be loaded to the transmitter.

A transmitted character consists of a start bit, the programmed

number of data and stop bits and an “address/data” bit. The parity

bit is used as the address or data indicator. The polarity of the A/D

bit is selected by setting MR1[2] to zero or one; zero indicates that

the current byte is data, while one indicates that the current byte is

addressed. The desired polarity of the A/D bit (parity) should be

programmed before

the TxFIFO is loaded.

The receiver should be enabled before the beginning of the first data

bit. The time required is dependent on the interrupt latency of the

slave receivers. The transmitter is able to start data immediately

after the address byte has been sent.

While in this mode, the receiver continuously looks at the received

data stream, whether it is enabled or disabled. If disabled, it sets the

RxRDY status bit and loads the character in the RxFIFO if the

received A/D bit is a one, but discards the received character if the

received A/D bit is a zero. If enabled, all received characters are

then transferred to the CPU via the RxFIFO. In either case, the data

bits are loaded in the data FIFO while the A/D bit is loaded in the

status FIFO position normally used for parity error (SR[5]). Framing

error, overrun error, and break detect operate normally whether or

not the receiver is enabled.

INPUT OUTPUT (I/O) PINS

There are 16 multi-use pins; four for each UART. These pins are

accessed and controlled via the Input Port Register (IPR), I/O Port

Control Register (I/OPCR), Input Port Change Register (IPCR), and

Output Port Register (OPR). They may be individually programmed

to be inputs or outputs. See Table 5.

I/O0x and I/O1x pins have change of state detectors. The change of

state detectors sample the input ports every 26.04µs (with the X1

clock at 3.686400MHz) and set the change bit in the IPCR if the pin

has changed since it was last read. Whether the pins are

programmed as inputs or outputs the change detectors still operate

and report changes accordingly. See the register descriptions of the

I/O ports for the detailed use of these features.

A read of the IPCR resets the I/O COS (Change Of State) detectors.

Interrupt Priority System

The interrupt control for the QUART has been designed to provide

very low interrupt service overhead for the controlling processor

while maintaining a high degree of flexibility in setting the

importance of interrupts generated in different functional blocks of

the device.

This is accomplished by allowing each function of the QUART (18

total) which may cause an interrupt to generate a variable numeric

code which contains the identity of the source, channel number and

severity level. This code is compared (at the X1 clock rate or the X1

clock rate divided by 2) to an interrupt threshold. When the

interrupting source generates a code that is numerically greater than

the interrupt threshold the IRQN is asserted

This is referred to as the bidding process. The winning bid contains,

in different fields, all the characteristics of the winning bidder. This

data may be used in several ways to steer the controlling processor

to the proper type and amount of service required (usually the

amount of service refers to the number of bytes written to the

transmitter or read from the receiver). Access to the winning bidder

is provided via the CIR (Current Interrupt Register), interrupt

vectors, modified interrupt vectors and Global registers.

NOTE: IRQN is essentially a level output. It will go active on an

interrupt condition and stays active until all interrupting sources are

serviced.

IRQN is designed to be an open drain active low level output. It will

go low under the control of the arbitration system and remain low

until the arbitration has determined that no more sources require

service.

When only one Rx or Tx is interrupting, it is possible to see the

IRQN assert more than once if, during an access to the FIFO, the

CEN input is inactive for more than two cycles of the X1 clock or X1

divide by 2 if that feature is enabled.

IACKN may be thought of as a special read input. Driving IACKN

low will update the CIR and then read the Interrupt Vector Register

or the Interrupt Vector Register modified by the CIR.

Philips Semiconductors Product data sheet

SC28C94Quad universal asynchronous receiver/transmitter (QUART)

2006 Aug 09

Functional Description of the Interrupt Arbitration

For the purpose of this description, a ‘source’ is any one of the 18

QUART circuits that may generate an interrupt. The QUART

contains eighteen sources which may cause an interrupt:

1. Four receiver data FIFO filled functions.

2. Four receiver BREAK detect functions.

3. Four transmitter FIFO space available functions.

4. Four “Change of State” detectors.

5. Two counter/timers.

The interrupt logic at each source produces a numeric code that

identifies its interrupt priority condition currently pending. This code

is compared to a programmable Interrupt Threshold via the

arbitration logic which determines if the IRQN should be asserted.

The arbitration logic only judges those possible interrupt sources

which have been allowed to bid via the IMR (Interrupt Mask

The arbitration logic produces a value which is the concatenation of

the channel number, interrupt type, FIFO fill level and user-defined

fields. The channel number and interrupt type fields are hardwired.

During the “bid arbitration” process all bids from enabled sources

are presented, simultaneously, to an internal interrupt bus. The

bidding system and formats are discussed in more detail in

following sections.

The interrupt arbitration logic insures that the interrupt with the

numerically largest bid value will be the only source driving the

interrupt bus at the end of the arbitration period. The arbitration

period follows the period of the X1 clock. The maximum speed is

4.0MHz. If a higher speed X1 clock is used then the X1 clock “divide

by 2” feature must be used.

The value of the winning bid determined during the arbitration cycle

is compared to the “Interrupt Threshold” contained in the ICR

(Interrupt Control Register). If the winning bid exceeds the value of

the ICR the IRQN is asserted.

Priority Arbitration and Bidding

Each of the five “types” of interrupts has slightly different “bid” value,

as follows:

Receivers

Transmitters

Break Detect

Change of State

Counter/Timer

# rcv’d rEr 1 1 Chan #

31112

0 # avail 1 0 Chan #

13 112

Programmable 1 0 0 Chan #

31112

Programmable 0 0 1 Chan #

31112

Programmable 1 0 1 Chan #

21112

SD00162

Please see “Interrupt Notes” at the end of this specification.

Bits shown above as ‘0’ or ‘1’ are hard-wired inputs to the arbitration

logic. Their presence allows determination of the interrupt type and

they insure that no bid will have a value of all zeros (a condition that

is indistinguishable from not bidding at all). They also serve to set a

default priority among the non-receive/transmit types when the

programmable fields are all zeros.

The channel number always occupies the two LSBs. Inclusion of

the channel number insures that a bid value generated will be

unique and that a single “winner” will drive the Interrupt Bus at the

end of the arbitration interval. The channel number portion of each

UARTs bid is hard-wired with UARTa being channel number 0 and

so forth.

As can be seen above, bits 4:2 of the winning bid value can be used

to identify the type of interrupt, including whether data was received

correctly or not. Like the Channel number field, these bits are

hard-wired for each interrupt source.

The “# rcv’d” and “# avail” fields indicate the number of bytes

present in the receiver FIFO and the number of empty bytes in the

transmitter FIFO, respectively.

NOTE: When there are zero bytes in the receiver’s FIFO, it does

NOT bid. Similarly, a full transmitter FIFO makes NO bid. In the

case where all bids have been disabled by the Interrupt Mask

Bus will return FFh. This value always indicates no interrupt source

is active and IRQN will be negated.

The high order bit of the transmitter “bid” is always zero. An empty

transmit FIFO is, therefore, fixed at a lower interrupt priority than a

1/2 full receive FIFO. Bit 4 of a receiver bid is the Receiver Error Bit

(RER). The RER is the OR of the parity, framing and overrun error

conditions. The RER does little to modify the priority of receiver

interrupts vs. transmitter interrupts. It is output to the Interrupt Bus

to allow inclusion of good data vs. problem data information in the

Current Interrupt Register.

The high order bits of bids for received break, CoS (Change of

State) and Counter/Timer events are all programmable. By

programming ones in these fields, the associated interrupt source

can be made more significant than most receiver and all transmitter

interrupts. Values near zero in these fields makes them lower

priority classes of interrupt.

The channel address for C/T ab will be encoded as channel B (01)

The channel address for C/T cd will be encoded as channel D (11)

As shown in Figure 7, the bid arbitration process is controlled by the

EVAL/HOLDN signal derived from the oscillator clock.

Receipt of an IACKN signal from the host MPU latches the latest

“winning bid” from the latched Interrupt Bus into the Current Interrupt

If the IACKN falling edge of Figure 7 occurs during EVAL time, the

result from the last arbitration (captured by the Interrupt Bus latches)

is stored in CIR. Otherwise, the next EVAL pulse is inhibited and the

value in the Interrupt Bus Latches is stored in CIR.

Clearing the Interrupt

Activities which change the state of the ISR will cause the IRQN to

assert or negate. In addition, the accessing of a global or local

RxFIFO or TxFIFO reduces the associated byte count for transmitter

and receiver data interrupts. If the byte count falls below the

threshold value, the interrupt request is withdrawn. Other interrupt

conditions are cleared when the interrupting source is cleared.

Once the interrupt is cleared, the programmable value lowered or its

byte count value reduced by one of the methods listed above, a

different bidder (or no bidder at all) will win the on-going arbitration.

When the winning bid drops below the Interrupt Threshold

Philips Semiconductors Product data sheet

SC28C94Quad universal asynchronous receiver/transmitter (QUART)

2006 Aug 09

Arbitration - Aftermath

At the end of the arbitration, i.e., the falling edge of EVAL, the

winning interrupt source is driving its Channel number, number of

bytes (if applicable) and interrupt type onto the Interrupt Bus. These

values are captured into a latch by the trailing edge of EVAL. The

output of this latch is used by the Interrupt Threshold comparator;

the winning value is captured into another set of latches called the

Current Interrupt Register (CIR) at the time of an Interrupt

Acknowledge cycle or execution of the “Update CIR” command.

The Current Interrupt Register and associated read logic is shown in

Figure 8. Interrupting channel number and the three bit interrupt

type code and FIFO fill level are readable via the Internal Data Bus.

The contents of the appropriate receiver or transmitter byte

“counter”, as captured at the time of IACKN assertion, make up bits

7:5 of the CIR. If the interrupt type stored in the Current Interrupt

CIR7:5 field will read as the programmable fields of their respective

bid formats.

The buffers driving the CIR to the DBUS also provide the means of

implementing the Global Interrupting Channel and Global Byte

Count Registers, described in a later section.

The winning bid channel number and interrupt type fields can also

be used to generate part of the Interrupt Vector, as defined by the

Interrupt Control Register.

Interrupt Context

The channel number of the winning “bid” is used by the address

decoders to provide data from the interrupting UART channel via a

set of Global pseudo-registers. The interrupt Global

pseudo-registers are:

1. Global Interrupting Byte Count

2. Global Interrupting Channel

3. Global Receive Holding Register

4. Global Transmit Holding Register

The first two Global “registers” are provided by Current Interrupt

number latched in CIR modifies address decoding so that the

Receive or Transmit Holding Register for the interrupting channel is

accessed during I/O involving the Global Receive and Transmit

Holding Registers. Similarly, for data interrupts from the transmitter

and receiver, the number of characters available for transfer to the

CPU or the number of transmit FIFO positions open is available by

reading the Global Interrupt Byte Count Register. For non-data

interrupts, a read of the Global Interrupt Byte Count Register yields

a value equal to the highest programmable filed.

In effect, once latched by an IACK or the Update CIR command, the

winning interrupt channel number determines the contents of the

global registers. All Global registers will provide data from the

interrupting UART channel.

Interrupt Threshold Calculation

The state of IRQN is determined by comparison of the winning “bid”

value to the Interrupt Threshold field of the Interrupt Control

The logic of the bidding circuit is such that when no interrupt source

has a value greater than the interrupt threshold then the interrupt is

not asserted and the CIR (Current Interrupt Register) is set to all

ones. When one or more of the 18 interrupt sources which are

enabled via the IMR (Interrupt Mask Register) exceed the threshold

then the interrupt threshold is effectively disconnected from the

bidding operation while the 18 sources now bid against each other.

The final result is that the highest bidding source will disable all

others and its value will be loaded to the CIR and the IRQN pin

asserted low. This all occurs during each cycle of the X1, X2 crystal

clock.

Table 2. Receiver FIFO Interrupt Fill Level

MR0[6] MR1[6] Interrupt Condition

1 or more bytes in FIFO (Rx RDY) default*

3 or more bytes in FIFO

6 or more bytes in FIFO

8 bytes in FIFO (Rx FULL)

For the receiver these bits control the number of FIFO positions

empty when the receiver will attempt to interrupt. After the reset the

receiver FIFO is empty. The default setting of these bits cause the

receiver to attempt to interrupt when it has one or more bytes in it.

Table 3. Transmitter FIFO Interrupt Fill Level

MR0[5] MR0[4] Interrupt Condition

8 bytes empty (Tx EMPTY) default*

4 or more bytes empty

6 or more bytes empty

1 or more bytes empty (Tx RDY)

For the transmitter these bits control the number of FIFO positions

empty when the receiver will attempt to interrupt. After the reset the

transmit FIFO has 8 bytes empty. It will then attempt to interrupt as

soon as the transmitter is enabled. The default setting of the MR0

bits (00) condition the transmitter to attempt to interrupt only when it

is competely empty. As soon as one byte is loaded, it is no longer

empty and hence will withdraw its interrupt request.

*These conditions, for interrupt purposes, make the RxFIFO look

like a 3 byte FIFO; the TxFIFO a 1 byte FIFO. This is to allow

software compatibility with previous Philips UART devices. Both

FIFOs accept 8 bytes of data regardless of this bit setting. Only the

interrupt is affected.

INTERRUPT NOTE ON 28C94:

For the receivers and transmitters, the bidding of any particular

unit may be held off unless one of four FIFO fill levels is

attained. This is done by setting the RxINT and TxINT bits in

MR0 and MR1 to non-zero values. This may be used to prevent

a receiver or transmitter from generating an interrupt even

though it is filed above the bid threshold. Although this is not

in agreement with the idea that each enabled interrupt source

bid with equal authority, it does allow the flexibility of giving

particular receiver or transmitters more interrupt importance

than others.

This may be used when the Interrupt Threshold is set at or

above 100000. Note than in this case the transmitter cannot

generate an interrupt. If the interrupt threshold MSBs were set

to 011

and

the ‘Receiver Interrupt Bits’ on the MR registers set

to a value other than 00 then the RxFIFO could not generate

and interrupt until it had 4, 6 or 8 bytes. This in effect partially

defeats the hardwired characteristic that the receiver interrupts

should have more importance than the transmitter. This

characteristic has been implemented by setting the MSB of the

transmitter bid to zero.

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SC28C94A1A,512

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UART Interface IC UART QUAD W/FIFO

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