SC28C94A1A,512 Datasheet SC28C94A1A,512, SC28C94A1A,518, SC28C94A1N,112 | P7-P9

Philips Semiconductors Product data sheet

SC28C94Quad universal asynchronous receiver/transmitter (QUART)

2006 Aug 09

FUNCTIONAL BLOCKS

The QUART is composed of four Philips Semiconductors

industry–standard UARTs, each having a separate transmit and

receive channel.

The Basic UART cells in the QUART are configured with 8-byte

Receive FIFOs and 8-byte Transmit FIFOs. Hardware supports

interrupt priority arbitration based on the number of bytes available

in the transmit and receive FIFOs, counter/timers, change of state

detectors, break detect or receiver error. Attempts to push a full

FIFO or pop an empty FIFO do not affect the count.

Baud Rate Generator

The baud rate generator used in the QUART is the same as that

used in other Philips Semiconductors industry standard UARTs. It

provides 18 basic Baud rates from 50 baud to 38,400 baud. It has

been enhanced to provide to provide other baud rates up to 230,400

baud based on a 3.6364MHz clock; with an 8.0MHz clock rates to

500K baud. Other rates are available by setting the BRG rate to high

at address 2D hex or setting Test 1 on at address 39 hex. See

Table 6. These two modes are controlled by writing 00 or 01 to the

addresses above. They are both set to 00 on reset. External Rx and

Tx clocks yield rates to 1MHz in the 16X mode.

BLOCK DIAGRAM

As shown in the block diagram, the QUART consists of: data bus

buffer, interrupt control, operation control, timing, and four receiver

and transmitter channels. The four channels are divided into two

different blocks, each block independent of the other.

Channel Blocks

There are two blocks (Block Diagram), each containing two sets of

receiver/transmitters. In the following discussion, the description

applies to Block A which contains channels a and b. However, the

same information applies to all channel blocks.

Data Bus Buffer

The data bus buffer provides the interface between the external and

internal data buses. It is controlled by the operation control block to

allow read and write operations to take place between the controlling

CPU and the QUART.

Operation Control

The operation control logic receives operation commands from the

CPU and generates appropriate signals to internal sections to

control device operation. It contains address decoding and read and

write circuits to permit communications with the microprocessor via

the data bus buffer. The functions performed by the CPU read and

write operations are shown in Table 1.

Mode registers (MR) 0, 1 and 2 are accessed via an address

counter. This counter is set to one (1) by reset or a command 1x to

the Command Register for compatibility with other Philips

Semiconductors software. It is set to 0 via a command Bx to the

Command Register (CR). The address counter is incremented with

each access to the MR until it reaches 2 at which time it remains at

2. All subsequent accesses to the MR will be to MR2 until the MR

counter is changed by a reset or an MR counter command.

The Mode Registers control the basic configuration of the UART

channels. There is one for each UART. (Transmitter/receiver pair)

Timing Circuits

The timing block consists of a crystal oscillator, a baud rate

generator, power up/down logic and a divide by 2 selector. Closely

associated with the timing block are two 16-bit counter/timers; one

for each DUART.

Oscillator

The crystal oscillator operates directly from a 3.6864MHz crystal

connected across the X1/CLK and X2 inputs with a minimum of

external components. If an external clock of the appropriate

frequency is available, it may be connected to X1/CLK. If an external

clock is used instead of a crystal, X1 must be driven and X2 left

floating as shown in Figure 14. The clock serves as the basic timing

reference for the baud rate generator (BRG), the counter/timer, and

other internal circuits. A clock frequency, within the limits specified in

the electrical specifications, must be supplied even if the internal

BRG is not used.

The X1 pin always supplies the clock for the baud rate generator.

The X1 pin also has a feature such that it may be divided by 2. The

divide by two mode must always be used whenever the X1 pin is

above 4MHz. The baud rate generator supplies the standard rates

when X1 is at 3.6864MHz. In the divide by 2 mode, all circuits

receive the divide by two clock except baud rate generator and I/O

pin change-of-state detectors. The use of a 7.3738MHz X1 clock

doubles standard baud rates.

Baud Rate Generator

The baud rate generator operates from the oscillator or external

clock input and is capable of generating 18 commonly used data

communications baud rates ranging from 50 to 38.4K baud. The

eighteen BRG rates are grouped in two groups. Eight of the 18 are

common to each group. The group selection is controlled by ACR[7].

See the Baud Rate Table 6. The clock outputs from the BRG are at

16X the actual baud rate. The counter/timer can be used as a timer

to produce a 16X clock for any other baud rate by counting down the

crystal clock or an external clock. The clock selectors allow the

independent selection, by the receiver and transmitter, of any of

these baud rates or an external timing signal.

Counter/Timer

The counter timer is a 16-bit programmable divider that operates in

one of three modes: counter, timer, time out. In the timer mode it

generates a square wave. In the counter mode it generates a time

delay. In the time out mode it monitors the time between received

characters. The C/T uses the numbers loaded into the

Counter/Timer Lower Register (CTLR) and the Counter/Timer Upper

There are two counter/timers in the QUART; one for each block.

The counter/timer clock source and mode of operation (counter or

timer) is selected by the Auxiliary Control Register bits 6 to 4

(ACR[6:4]). The output of the counter/timer may be used for a baud

rate and/or may be output to the I/O pins for some external function

that may be totally unrelated to data transmission. The

counter/timer also sets the counter/timer ready bit in the Interrupt

Status Register (ISR) when its output transitions from 1 to 0.

A register read address (see Table 1) is reserved to issue a start

counter/timer command and a second register read address is

reserved to issue a stop command. The value of D(7:0) is ignored.

The START command always loads the contents of CTUR, CTLR to

the counting registers. The STOP command always resets the

ISR(3) bit in the interrupt status register.

Timer Mode

In the timer mode a symmetrical square wave is generated whose

half period

is equal in time to division of the selected counter/timer

clock frequency by the 16-bit number loaded in the CTLR CTUR.

Thus, the frequency of the counter/timer output will be equal to the

counter/timer clock frequency divided by twice the value of the

CTUR CTLR. While in the timer mode the ISR bit 3 (ISR[3]) will be

Philips Semiconductors Product data sheet

SC28C94Quad universal asynchronous receiver/transmitter (QUART)

2006 Aug 09

set each time the counter/timer transitions from 1 to 0. (High to low)

This continues regardless of issuance of the stop counter command.

ISR[3] is reset by the stop counter command. NOTE: Reading of

the CTU and CTL registers in the timer mode is not meaningful.

When the C/T is used to generate a baud rate

and

the C/T is

selected through the CSR then the receivers and/or transmitter will

be operating in the 16x mode. Calculation for the number ‘n’ to

program the counter timer upper and lower registers is shown below.

n=2 x 16 x Baud rate desired/(C/T Clock Frequency

Often this division will result in a non-integer number; 26.3 for

example. One can only program integer numbers to a digital divider.

Therefore 26 would be chosen. This gives a baud rate error of

0.3/26.3 which is 1.14%; well within the ability of the asynchronous

mode of operation.

Counter Mode

In the counter mode the counter/timer counts the value of the CTLR

CTUR down to zero and then sets the ISR[3] bit and sets the

counter/timer output from 1 to 0. It then rolls over to 65,365 and

continues counting with no further observable effect.

Reading the C/T in the counter mode outputs the present state of

the C/T. If the C/T is not stopped, a read of the C/T may result in

changing data on the data bus.

Timeout Mode

The timeout mode uses the received data stream to control the

counter. The time-out mode forces the C/T into the timer mode.

Each time a received character is transferred from the shift register

to the RxFIFO, the counter is restarted. If a new character is not

received before the counter reaches zero count, the counter ready

bit is set, and an interrupt can be generated. This mode can be used

to indicate when data has been left in the Rx FIFO for more than the

programmed time limit. If the receiver has been programmed to

interrupt the CPU when the receive FIFO is full, and the message

ends before the FIFO is full, the CPU will not be interrupted for the

remaining characters in the RxFIFO.

By programming the C/T such that it would time out in just over one

character time, the above situation could be avoided. The

processor would be interrupted any time the data stream had

stopped for more than one character time. NOTE: This is very

similar to the watch dog time of MR0. The difference is in the

programmability of the delay time and that the watchdog timer is

restarted by either a receiver load to the RxFIFO or a system read

from it.

This mode is enabled by writing the appropriate command to the

command register. Writing an ‘Ax’ to CRA or CRB will invoke the

timeout mode for that channel. Writing a ‘Cx’ to CRA or CRB will

disable the timeout mode. Only one receiver should use this mode

at a time. However, if both are on, the timeout occurs after both

receivers have been inactive for the timeout period. The start of the

C/T will be on the logical or of the two receivers.

The timeout mode disables the regular START/STOP counter

commands and puts the C/T into counter mode under the control of

the received data stream. Each time a received character is

transferred from the shift register to the RxFIFO, the C/T is stopped

after one C/T clock, reloaded with the value in CTUR and CTLR and

then restarted on the next C/T clock. If the C/T is allowed to end the

count before a new character has been received, the counter ready

bit, ISR[3], will be set. If IMR[3] is set, this will generate an interrupt.

Since receiving a character restarts the C/T, the receipt of a

character after the C/T has timed out will clear the counter ready bit,

ISR[3], and the interrupt. Invoking the ‘Set Timeout Mode On’

command, CRx=‘Ax’, will also clear the counter ready bit and stop

the counter until the next character is received.

The counter timer is controlled with six commands: Start/Stop C/T,

Read/Write Counter/Timer lower register and Read/Write

Counter/Timer upper register. These commands have slight

differences depending on the mode of operation. Please see the

detail of the commands under the CTLR CTUR Register

descriptions.

Time–out Mode Caution

When operating in the special time–out mode, it is possible to

generate what appears to be a “false interrupt”, i.e., an interrupt

without a cause. This may result when a time-out interrupt occurs

and then, BEFORE the interrupt is serviced, another character is

received, i.e., the data stream has started again. (The interrupt

latency is longer than the pause in the data strea.) In this case,

when a new character has been receiver, the counter/timer will be

restarted by the receiver, thereby withdrawing its interrupt. If, at this

time, the interrupt service begins for the previously seen interrupt, a

read of the ISR will show the “Counter Ready” bit not set. If nothing

else is interrupting, this read of the ISR will return a x’00 character.

This action may present the appearance of a spurious interrupt.

Receiver and Transmitter

The QUART has four full-duplex asynchronous

receiver/transmitters. The operating frequency for the receiver and

transmitter can be selected independently from the baud rate

generator, the counter/timer, or from an external input.

Registers associated with the communications channel are the

mode registers (MR0, MR1 and MR2) Clock Select Register (CSR),

Command Register (CR), Status Register (SR), Transmit FIFO

(TxFIFO), and the Receive FIFO (RxFIFO). The transmit and

receive FIFOs are each eight characters deep. The receive FIFO

also stores three status bits with each character.

Transmitter

The transmitter accepts parallel data from the CPU and converts it

to a serial bit stream on the TxD output pin. It automatically sends a

start bit followed by the programmed number of data bits, an

optional parity bit, and the programmed number of stop bits. The

least significant bit is sent first. Following the transmission of the

stop bits, if a new character is not available in the TxFIFO, the TxD

output remains high and the TxEMT bit in the SR will be set to 1.

Transmission resumes and the TxEMT bit is cleared when the CPU

loads a new character in the TxFIFO. In the 16X clock mode, this

also re-synchronizes the internal 1X transmitter clock so that

transmission of the new character begins with minimum delay.

If the transmitter is disabled it continues operating until the character

currently being transmitted and any characters in the TxFIFO,

including parity and stop bits, have been transmitted. New data

cannot be loaded to the TxFIFO when the transmitter is disabled.

The transmitter can be forced to send a break (a continuous low

condition) by issuing a START BREAK command via the CR

transmitter reset..

TxFIFO

The TxFIFO empty positions are encoded as a three bit number for

presentation to the bidding logic. The coding will equal the number

of bytes that remain to be filled. That is, a binary number of 101 will

mean five bytes may be loaded; 111 means 7, etc. Eight positions

will be indicated by a binary 111

and

the FIFO empty bit will be set.

Receiver

The receiver accepts serial data on the RxD pin, converts the serial

input to parallel format, checks for start bit, stop bit, parity bit (if any),

Philips Semiconductors Product data sheet

SC28C94Quad universal asynchronous receiver/transmitter (QUART)

2006 Aug 09

or break condition, and presents the assembled character to the

CPU via the receiver FIFO.

The receiver operates in two modes: the 1X and 16X. The 16X

mode is the more robust of the two. It allows the receiver to

establish a phase relation to the remote transmitter clock within 1/16

of a bit time and also allows validation of the start bit. The 1X mode

does not validate the start bit and assumes that the receiver clock

rising edge is centered in the data bit cell. The use of the 1X mode

implies that the transmitter clock is available to the receiver.

When operating in the 16X mode and after the receiver has been

enabled the receiver state machine will look for a high to low

transition on the RxD input. The detection of this transition will cause

the divider being driven by the 16X clock to be reset to zero and

continue counting. When the counter reaches 7 the RxD input is

sampled again and if still low a valid START BIT will be detected. If

the RxD input is high at count 7 then an invalid start bit will have

been sensed and the receiver will then look for another high to low

transition and begin validating again.

When a valid start bit is detected the receiver state machine allows

the 16X divider circuit to continue counting 0 to 15. Each time the

receiver passes count 7 (the theoretical center of the bit time)

another data bit is clocked into the receiver shift register until the

proper number of bits have been received including the parity bit, if

used, and 1/2 stop bit. After the STOP BIT is detected the receiver

state machine will wait until the next falling edge of the 1X clock and

then clock the assembled character and its status bits into the

receiver FIFO on the next rising edge of the 1X clock. The delay

from the detection of the STOP BIT to the loading of the character to

the RxFIFO will be from one half to one and one half X1 crystal

clock periods, or twice that if X1/2 is used. Receiver Status Register

bits for FIFO READY, FIFO FULL, parity error, framing error, break

detect will also set at this time. The most significant bits for data

characters less than eight bits will be set to zero.

After the stop bit is detected, the receiver will immediately look for

the next start bit. However, if a non-zero character was received

without a stop bit (i.e. framing error) and RxD remains low for

one-half of the bit period after the stop bit was sampled, then the

receiver operates as if a new start bit transition had been detected at

that point (one-half bit time after the stop bit was sampled). The

parity error, framing error and overrun error (if any) are strobed into

the SR at the received character boundary, before the RxRDY

status bit is set.

If a break condition is detected (RxD is low for the entire character

including the stop bit), only one character consisting of all zeros will

be loaded in the FIFO and the received break bit in the SR is set to

1. The “Change of Break” bit in the ISR at position 2 or 6 is also set

at this time. Note that the “Change of Break” bit will set again when

the break condition terminates. The RxD input must return to high

for two (2) clock edges of the X1 crystal clock for the receiver to

recognize the end of the break condition and begin the search for a

start bit. This will usually require a high time of one X1 clock

period or 3 X1 edges since the clock of the controller is not

synchronous to the X1 clock.

NOTE: If the RxD input is low when the receiver is enabled and

remains low for at least 9/16 of a bit time a valid start bit will be

seen and data (probably random) will be clocked into the

receiver FIFO. If the line remains low for a full character time

plus a stop bit then a break will be detected.

Receiver FIFO

The RxFIFO consists of a first-in-first-out (FIFO) with a capacity of

eight characters. Data is loaded from the receive shift register into

the top-most empty position of the FIFO. The RxRDY bit in the

status register (SR) is set whenever one or more characters are

available to be read; a FFULL status bit is set if all eight stack

positions are filled with data. The number of filled positions is

encoded into a 3-bit value. This value is sent to the interrupt bidding

logic where it is used to generate an interrupt. A read of the RxFIFO,

outputs the data at the top of the FIFO. After the read cycle, the data

FIFO and its associated status bits are ‘popped’ thus emptying a

FIFO position for new data.

NOTE: The number of filled positions in the RxFIFO is coded

as actual number filled positions. Seven filled will be coded as

7. Eight filled positions will be coded as 7

and

the RxFIFO full

status bit will be set.

Status

In addition to the data word, three status bits (parity error, framing

error, and received break) are appended to each data character in

the FIFO. Status can be provided in two ways, as programmed by

the error mode control bit in the mode register. In the ‘character’

mode, status is provided on a character-by-character basis: the

status applies only to the character at the top of the FIFO. In the

‘block’ mode, the status provided in the SR for these three bits is the

logical OR of the status for all characters coming to the top of the

FIFO since the last reset error command was issued. In either

mode, reading the SR does not affect the FIFO. The FIFO is

‘popped’ only when the RxFIFO is read. Therefore, the SR should

be read prior to reading the corresponding data character.

If the FIFO is full when a new character is received, that character is

held in the receive shift register until a FIFO position is available. If

an additional character is received while this state exists, the

contents of the FIFO are not affected: the character previously in the

shift register is lost and the overrun error status bit, SR[4], will be set

upon receipt of the start bit of the new (overrunning) character.

Watchdog Timer

A “watchdog” timer is associated with each receiver. Its interrupt is

enabled by MR0[7]. The purpose of this timer is alerting the control

processor that characters are in the RxFIFO which have not been

read and/or the datastream has stopped. This situation may occur

at the end of a transmission when the last few characters received

are not sufficient to cause an interrupt.

This counter times out after 64 bit times. It is reset each time a

character is transferred from the Receive shift register to the

RxFIFO or a read of the RxFIFO is executed.

Each receiver is equipped with a watchdog timer. This timer is

enabled by MR0[7] and counts 64 RxC1X clocks. Its purpose is to

alert the controlling CPU that data is in the FIFO which has not been

read. This situation may occur at the end of a message when the

last group of characters was not long enough to cause an interrupt.

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SC28C94A1A,512

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Description:

UART Interface IC UART QUAD W/FIFO

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