Philips Semiconductors Product data sheet
SC28C94Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
30
RESET
t
RES
SD00169
Figure 10. Reset Timing
RDN
CEN
I/O as Output
I/O as Input
t
PS
t
PH
t
PD
t
PD
WRN
OLD DATA NEW DATA
I/O PINS MUST BE STABLE FOR NON-CHANGING BUS DATA DURING THE READ.
NOTE: I/O PIN DATA IS NOT LATCHED
SD00170
Figure 11. I/O Port Timing
WRN
INTERRUPT
1
OUTPUT
RDN
INTERRUPT
1
OUTPUT
V
M
t
IR
t
IR
V
OL
+0.5V
V
OL
+0.5V
V
OL
V
OL
NOTES:
1. INCLUDES I/O WHEN USED AS TxRDY or RxDY/FFULL OUTPUTS AS WELL AS IRQN.
2. THE TEST FOR OPEN DRAIN OUTPUTS IS INTENDED TO GUARANTEE SWITCHING OF THE OUTPUT TRANSISTOR. MEASUREMENT OF THIS RESPONSE IS
REFERENCED FROM THE MIDPOINT OF THE SWITCHING SIGNAL, V
M
, TO A POINT 0.5V ABOVE V
OL
. THIS POINT REPRESENTS NOISE MARGIN THAT AS-
SURES TRUE SWITCHING HAS OCCURRED. BEYOND THIS LEVEL, THE EFFECTS OF EXTERNAL CIRCUITRY AND TEST ENVIRONMENT ARE PRONOUNCED
AND CAN GREATLY AFFECT THE RESULTANT MEASUREMENT.
SD00171
Figure 12. Interrupt Timing
