Philips Semiconductors Product data sheet
SC28C94Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
31
C1 and C2 should be chosen according to the
crystal manufacturer’s specification.
C1 and C2 values will include any parasitic
capacitance of the wiring.
X1/CLK
CTCLK
RxC
TxC
t
CLK
t
CTC
t
Rx
t
Tx
t
CLK
t
CTC
t
Rx
t
Tx
+5V
1K required for
TTL gate.
X1
X2
C1 = C2 = 24pF FOR C
L
= 20PF
X1
X2
3.6864MHz
3pF
4pF
50 KOHMs
TO
150 KOHMs
26C94
NOTES:
C1 and C2 should be based on manufacturer’s specification.
X1 and X2 parasitic capacitance IS 1-2pF AND 3-5pF, respectively.
GAIN: at 4MHz 8 to 14db; at 8MHz 2 to 6db
PHASE: at 4MHz 272° to 276°; at 8MHz 272° to 276°
TYPICAL CRYSTAL SPECIFICATION
FREQUENCY: 2 – 4MHZ
LOAD CAPACITANCE (C
L
): 12 – 32pF
TYPE OF OPERATION: PARALLEL RESONANT, FUNDAMENTAL MODE
NC
C1
C2
MUX
To
remainder
of circuit
÷ 2
38.4kHz CLOCK
BRG
TO I/O CHANGE-OF-STATE DETECTORS
22
STANDARD
BAUD
RATES
SD00172
POWER DOWN
Figure 13. Clock Timing
TxC
(INPUT)
TxD
TxC
(1X OUTPUT)
1 BIT TIME
(1 OR 16 CLOCKS
t
TCS
t
TXD
SD00173
Figure 14. Transmit Clock Timing
Philips Semiconductors Product data sheet
SC28C94Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
32
RxC
(1X INPUT)
RxD
t
RXS
t
RXH
SD00174
Figure 15. Receive Clock Timing
TxD D1 D2 D3 BREAK D4 D6
TRANS-
MITTER
ENABLED
TxRDY
(SR2)
WRN
CTSN
1
(I/O0)
(I/O1)
RTSN
2
D1 D2 D3 START
BREAK
D4 STOP
BREAK
D5 WILL
NOT BE
TRANSMITTED
D6
CR[7:4] = 1010
CR[7:4] = 1010
NOTES:
1. TIMING SHOWN FOR MR2[4] = 1.
2. TIMING SHOWN FOR MR2[5] = 1.
MR0(5:4) = 00
SD00175
Figure 16. Transmitter Data Timing
Philips Semiconductors Product data sheet
SC28C94Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
33
D1 D2 D9 D10 D11 D12 D13D3RxD
RECEIVER
ENABLED
RxRDY
(SR0)
FFULL
(SR1)
RxRDY/
RDN
OVERRUN
(SR4)
RTS
1
I/O1
NOTES;
1. TIMING SHOWN FOR MR1[7] = 1.
2. DEFAULT: I/O1 IS RTS AND IOPCR(5:4) 01
FFULL
ISR(1)
I/O1 = 1 or (CR[7:4] = 1010)
RESET BY
COMMAND
D10 WILL
BE LOST
SD SD
SD
SD
D2
D3 D10
D1
S = STATUS
D = DATA
D2
D10 WILL BE
OVERWRITTEN
BY D11, 12, ETC
SD00176
Figure 17. Receiver Data Timing
MASTER STATION
TxD
TRANSMITTER
ENABLED
TxRDY
(SR2)
CEN
(WRITE]
PERIPHERAL STATION
RxD
RECEIVER
ENABLED
RxRDY
(SR0)
RDN/WRN
ADD#1 1 D0 0 ADD#2 1
BIT 9 BIT 9 BIT 9
BIT 9 BIT 9 BIT 9 BIT 9 BIT 9
MR1 [4:3] = 11
MR1 [2] = 1
ADD#1 MR1 [2] = 0 D0 MR1 [2] = 1 ADD#2
0 ADD#1 1 D0 0 ADD#2 1 0
MR1 [4:3] = 11
ADD#1
D0
SD
S = STATUS
D = DATA
SD
ADD#2
NOTE: TIMING SHOWN FOR FIFO POWER-UP DEFAULT
SD00177
Figure 18. Wake-Up Mode

SC28C94A1A,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC UART QUAD W/FIFO
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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