Philips Semiconductors Product data sheet
SC28C94Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
23
Registers of the Interrupt System
The CIR, and “Global” registers are updated with the IACKN signal
or from the “Update CIR” command at hex address 2A. These
registers are not updated when IRQN is asserted since there could
be a long time between the assertion of IRQN and the start of the
interrupt service routine. (See notes following this section).
Current Interrupt Register (CIR)
# Bytes
Type Chan #
3 3 2
The Channel # field indicates which of the four UARTs has the
highest priority interrupt currently outstanding, while the Type field
indicates its source within the UART. The Type field is encoded as
follows:
000 No Interrupt
001 Change of State
x10 Transmit available
011 Receive available, no error
100 Receiver break change
101 Counter/Timer
111 Receive available, w/errors
With Type = x11, the # Bytes field indicates the count of received
bytes available for reading, while with Type = x10 it indicates the
number of bytes that can be written to the transmit FIFO.
The CIR is Read only at address 28H.
Global Interrupt Byte Count (GIBC)
00000
# Bytes
5 3
The GIBC is not an actual register but simply outputs the interrupting
UART’s transmit or receive byte counter value. The count, accurate
at the time IACKN asserts, is captured in the CIR. The high order 5
bits are read as ‘0’. The GIBC is read only at address 2AH.
Global RxFIFO (GRxFIFO)
Received Data
8
If a receiver is not the cause of the current interrupt, a read of the
Global RxFIFO will yield a byte containing all ones and NONE of the
UART channels’ receive FIFOs will be popped. (IMPORTANT)
The GRxFIFO is Read only at address 2BH.
Global TxFIFO (GTxFIFO)
Data to be Sent
8
If a transmitter is not the cause of the current interrupt, a write to the
Global TxFIFO has no effect.
The GTxFIFO is Write only at address 2BH.
Global Interrupting Channel (GICR)
000000
Chan #
6 2
Like the other Global pseudo-registers no hardware register exists.
The Channel number field of the Current Interrupt Register padded
with leading zeros is output as the GICR. The GICR is Read only at
address 29H.
C/Tab indicated by Channel code B 01
C/Tcd indicated by Channel code D 11
Interrupt Control (ICR)
Threshold
IVC
6 2
The Threshold Field is used by the interrupt comparator to
determine if a winning interrupt “bid” should result in interrupting the
host MPU. The threshold field resets to 00.
The IVC field controls what kind of vector the QUART returns to the
host MPU during an Interrupt Acknowledge cycle:
00 Output contents of Interrupt Vector Register
01 Output 6 MSBs of IVR and Channel number as 2 LSBs
10 Output 3 MSBs of IVR, Interrupt Type and Channel number
11 Disable generation of vector during IACK cycle.
Returns hex’FF during an IACKN cycle.
The IVC field reset to 00. The ICR is read/write at address 2CH.
Bidding Control Registers (BCRs)
Received Break
State Change C/T
3 3 2
This register is a transparent latch. It must be set to ensure the
expected operation of the arbitration system. The 3 MSBs
determine the priority of Received Break Interrupts; they are reset to
000.
Bits 4:2 determine the priority of Change of Input State interrupts,
and are reset to 00.
BCR Counter/Timer bits reset to 00.
There is one BCR per UART channel; they can be read or written at
addresses 20-23H.
Interrupt Vector (IVR)
The 8 bits of the interrupt vector
Interrupt Vector (IVR-Modified)
Always Used with IVC = 0x w/IVC = 01 or 10
3 3 2
Holds the constant bits of the interrupt acknowledge vector. As
shown, the three MSBs are always used, while the less significant
bits can be replaced by the interrupt type code and/or Channel code
bits contained in the CIR. The IVR is write only at address 29H.
